- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379060 > CY7C1333 (Cypress Semiconductor Corp.) 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) PDF資料下載
參數(shù)資料
| 型號： | CY7C1333 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| 中文描述： | 64Kx32流過式的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的64Kx32流通式的SRAM） |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | CY7C1333 |
64Kx32 Flow-Thru SRAM with NoBL Architecture
Functional Description
CY7C1333
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 4, 1999
Features
Pin compatible and functionally equivalent to ZBT
device MT55L64L32F
Supports 66-MHz bus operations with zero wait states
—Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use OE
Registered inputs for Flow-Through operation
Byte Write capability
64K x 32 common I/O architecture
Single 3.3V power supply
Fast clock-to-output times
—12.0 ns (for 66-MHz device)
—14.0 ns (for 50-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100-pin TQFP package
Burst Capability—linear or interleaved burst order
Low (16.5 mW) standby power
The CY7C1333 is a 3.3V, 64K by 32 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1333 is equipped with the
advanced No Bus Latency (NoBL) logic required to en-
able consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in sys-
tems that require frequent Write-Read transitions. The
CY7C1333 is pin/functionally compatible to ZBT SRAM
MT55L64L32F.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which, when deasserted, sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 12.0 ns (66-MHz
device).
Write operations are controlled by the four Byte Write Select
(BWS
[0:3]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
CLK
A
[15:0]
CEN
CE
1
CE
2
WE
BWS
CE
OE
64KX32
MEMORY
ARRAY
Logic Block Diagram
DQ
[31:0]
DatD
Q
CE
CONTROL
and WRITE
LOGIC
3
[3:0]
ADV/LD
32
32
32
16
16
32
Mode
Selection Guide
7C1333-66
7C1333-50
Maximum Access Time (ns)
12.0
14.0
Maximum Operating Current (mA)
Commercial
310
260
Maximum CMOS Standby Current (mA)
Commercial
5.0
5.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1334 | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| CY7C1335 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲器 RAM) |
| CY7C1336 | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
| CY7C1337 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲器 RAM) |
| CY7C1338G-117AXI | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1333-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C133-35JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 35ns 68-Pin PLCC |
| CY7C1333-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1333H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 2MBIT 64KX32 6.5NS 100TQFP - Bulk |
| CY7C1334-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。