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參數(shù)資料
| 型號(hào)： | CY7C1336 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
| 中文描述： | 64K的× 32同步流動(dòng)，通過3.3V的高速緩存內(nèi)存（3.3 64K的× 32同步流通式高速緩沖內(nèi)存） |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 189K |
| 代理商： | CY7C1336 |
PRELIMINARY
64K x 32 Synchronous Flow-Through 3.3V Cache RAM
CY7C1336
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
March 3, 1999
36
Features
Supports 66-MHz microprocessor cache systems with
zero wait states
64K by 32 common I/O
Low Standby Power (1.65 mW, L version)
Fast clock-to-output times
—7.5 ns (117-MHz version)
Two-bit wraparound counter supporting either inter-
leaved or linear burst sequence
Separate processor and controller address strobes
provide direct interface with the processor and external
cache controller
Synchronous self-timed write
Asynchronous Output Enable
3.3V I/Os
JEDEC-standard pinout
100-pin TQFP packaging
ZZ “sleep” mode
Logic Block Diagram
Functional Description
The CY7C1336 is a 3.3V 64K by 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
7.5 ns (117-MHz version). A 2-bit On-Chip Counter captures
the first address in a burst and increments the address auto-
matically for the rest of the burst access.
The CY7C1336 allows both interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the ad-
dress advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous Chip Enable input and
an asynchronous Output Enable input provide easy control for
bank selection and output three-state control.
CLK
ADV
ADSC
ADSP
A
[15:0]
GW
BWE
BW
3
BW
0
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
DQ[31:24]
ADDRESS
REGISTER
D
Q
RINPUT
CLK
64KX32
MEMORY
ARRAY
Q
0
Q
1
Q
D
CE
CE
CLR
SLEEP
DQ[23:16]
D
Q
D
Q
BDQ[15:8]
BDQ[7:0]
D
Q
ENABLE
REGISTER
CLK
D
Q
32
32
16
14
14
16
(A
0
,A
1
)
2
MODE
DQ
[31:0]
BW
1
BW
2
Selection Guide
7C1336–117
7C1336L-117
7.5
300
270
5.0
7C1336–100
7C1336L-100
8.0
260
235
5.0
7C1336–66
7C1336L-66
9.0
260
235
5.0
Maximum Access Time (ns)
Maximum Operating Current
(mA)
Maximum Standby Current (mA)
Pentium is a registered trademark of Intel Corporation.
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1336F-117AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 2M-Bit 64K x 32 7.5ns 100-Pin TQFP |
| CY7C1336H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 2MBIT 64KX32 6.5NS 100TQFP - Bulk |
| CY7C1338B-100AC | 功能描述:IC SRAM 4MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1338B-100ACT | 制造商:Cypress Semiconductor 功能描述:Cache Mem 4M-Bit 3.3V SRAM 100-Pin TQFP T/R |
| CY7C1338B-100AXC | 制造商: 功能描述: 制造商:undefined 功能描述: |
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