- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379060 > CY7C1334 (Cypress Semiconductor Corp.) 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1334 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| 中文描述： | 64Kx32流過(guò)式的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的64Kx32流通式的SRAM） |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大小： | 184K |
| 代理商： | CY7C1334 |
64Kx32 Pipelined SRAM with NoBL Architecture
CY7C1334
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 6, 1999
Features
Pin compatible and functionally equivalent to ZBT
device MT55L64L32P
Supports 133-MHz bus operations with zero wait states
—Data is transferred on every clock
Internally self-timed output buffer control to eliminate
the need to use OE
Fully registered (inputs and outputs) for pipelined
operation
Byte Write Capability
64K x 32 common I/O architecture
Single 3.3V power supply
Fast clock-to-output times
—4.2 ns (for 133-MHz device)
—5.0 ns (for 100-MHz device)
—7.0 ns (for 80-MHz device)
—10.0 ns (for 50-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100-pin TQFP package
Burst Capability—linear or interleaved burst order
Low (16.5 mW) standby power
Functional Description
The CY7C1334 is a 3.3V, 64K by 32 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1334 is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of the SRAM, especially in systems that require frequent
Write-Read transitions.The CY7C1334 is pin/functionally com-
patible to ZBT SRAM MT55L64L32P
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
4.2 ns (133-MHz device).
Write operations are controlled by the four Byte Write Selects
(BWS
[0-3]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
.
No Bus Latency and NoBL are trademarks of Cypress Semiconductor.
ZBT is a trademark of Integrated Device Technology.
CLK
A
[15:0]
CEN
CE
1
CE
2
WE
BWS
CE
OE
O
64KX32
MEMORY
ARRAY
C
Logic Block Diagram
DQ
[31:0]
DatD
Q
CE
CONTROL
and WRITE
LOGIC
3
[3:0]
R
a
ADV/LD
32
32
32
16
16
32
Selection Guide
7C1334-133
7C1334-100
7C1334-80
7C1334-50
Maximum Access Time (ns)
4.2
5.0
7.0
10
Maximum Operating Current (mA)
Commercial
400
360
310
260
Maximum CMOS Standby Current (mA)
Commercial
5.0
5.0
5.0
5.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1335 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| CY7C1336 | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
| CY7C1337 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| CY7C1338G-117AXI | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
| CY7C1338G-133BGXI | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1334-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1334-50ACT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1334-80AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1334H-166AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 64Kx32 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C133-55JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 55ns 68-Pin PLCC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。