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參數(shù)資料
| 型號： | CY7C1318AV18-200BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 1M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 228K |
| 代理商： | CY7C1318AV18-200BZC |
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 17 of 20
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12) 11010100010000101 11010100010010101 11010100010100101 Defines the type of SRAM.
Cypress JEDEC ID (11:1)
00000110100
00000110100
Value
Description
CY7C1316AV18
001
CY7C1318AV18
001
CY7C1320AV18
001
Version number.
00000110100
Allows unique identification of
SRAM vendor.
Indicate the presence of an ID
register.
ID Register Presence (0)
1
1
1
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size
3
1
32
107
Instruction Codes
Instruction
EXTEST
IDCODE
Code
000
001
Description
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
Boundary Scan Order
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Bump ID
6R
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
9M
9N
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
10G
9G
Boundary Scan Order
(continued)
Bit #
Bump ID
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1318AV18-250BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320AV18-167BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1316AV18-200BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320AV18-200BZC | IC MUX/DEMUX DIFF 42-TQFN |
| CY7C1316AV18-250BZC | PCI-Express Gen-2, 2-lane (4- channel), differential 2:1 mux/demux with Bypass. Single enable, 1.8V |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1318AV-200BZCES | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1318BV18-167BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V COM DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1318BV18-200BZI | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V IND DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1318BV18-250BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V COM DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1318BV18-250BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 18MBIT 1MX18 4NS 165FBGA - Bulk |
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