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參數(shù)資料
| 型號(hào)： | CY7C1320AV18-200BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | IC MUX/DEMUX DIFF 42-TQFN |
| 中文描述： | 512K X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁(yè)數(shù)： | 1/20頁(yè) |
| 文件大小： | 228K |
| 代理商： | CY7C1320AV18-200BZC |
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18-Mbit DDR-II SRAM 2-Word
Burst Architecture
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Cypress Semiconductor Corporation
Document #: 38-05499 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 29, 2005
Features
18-Mb density (2M x 8, 1M x 18, 512K x 36)
250-MHz clock for high bandwidth
2-Word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two output clocks (C and C) account for clock skew
and flight time mismatching
Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–V
DD
)
13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix)
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1316AV18 – 2M x 8
CY7C1318AV18 – 1M x 18
CY7C1320AV18 – 512K x 36
Functional Description
The CY7C1316AV18/CY7C1318AV18/CY7C1320AV18 are
1.8V Synchronous Pipelined SRAM equipped with DDR-II
architecture. The DDR-II consists of an SRAM core with
advanced synchronous peripheral circuitry and a 1-bit burst
counter. Addresses for Read and Write are latched on
alternate rising edges of the input (K) clock. Write data is regis-
tered on the rising edges of both K and K. Read data is driven
on the rising edges of C and C if provided, or on the rising edge
of K and K if C/C are not provided. Each address location is
associated with two 8-bit words in the case of CY7C1316AV18
that burst sequentially into or out of the device. The burst
counter always starts with a “0” internally in the case of
CY7C1316AV18. On CY7C1318AV18 and CY7C1320AV18,
the burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1318AV18 and two 36-bit words in the case of
CY7C1320AV18 sequentially into or out of the device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) enable maximum system clocking
and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1316AV18)
CLK
Gen.
A
(19:0)
K
K
Control
Logic
Address
Register
R
Read Data Reg.
R/W
BWS
[1:0]
DQ
[7:0]
Output
Logic
Control
Reg.
Reg.
Reg.
8
8
16
8
V
REF
W
8
C
C
8
LD
20
1
1
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1316AV18-250BZC | PCI-Express Gen-2, 2-lane (4- channel), differential 2:1 mux/demux with Bypass. Single enable, 1.8V |
| CY7C1320AV18-250BZC | IC MUX/DEMUX PCI-EX 42TQFN |
| CY7C1318AV18-167BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1324 | 3.3V 128K x 18 Synchronous Cache RAM(3.3V 128K x 18 同步高速緩沖存儲(chǔ)器 RAM) |
| CY7C1325F | 4-Mb (256K x 18) Flow-Through Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1320BV18-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1320BV18-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1320BV18-167BZI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1320BV18200BZC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin FBGA |
| CY7C1320BV18-200BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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