參數(shù)資料
型號(hào): CY7C1316BV18
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM)
中文描述: 18兆位的DDR - II SRAM的2字突發(fā)架構(gòu)(2字突發(fā)結(jié)構(gòu),18 -兆位的DDR - II SRAM的)
文件頁(yè)數(shù): 24/28頁(yè)
文件大?。?/td> 469K
代理商: CY7C1316BV18
CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Document Number: 38-05621 Rev. *C
Page 24 of 28
Switching Waveforms
[28, 29, 30]
Notes:
28.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
29.Output are disabled (High-Z) one clock cycle after a NOP.
30.In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
READ
2
READ
8
READ
3
NOP
4
NOP
5
WRITE
7
WRITE
6
NOP
1
9
10
Q40
tKHCH
tCO
t
tHC
t
tHA
tSD
tHD
tKHCH
tSD
tHD
DON’T CARE
UNDEFINED
tCLZ
tDOH
tCHZ
SC
tKH
tKHKH
tKL
tCYC
A0
D20
D21
D30
D31
Q00
Q11
Q01
Q10
A1
A2
A3
A4
Q41
tCCQO
tCQOH
tCCQO
tCQOH
tKL
tCYC
K
K
LD
R/W
A
DQ
C
C#
CQ
CQ#
SA
tKH
tKHKH
t
CQD
t
CQDOH
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CY7C1318BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結(jié)構(gòu),18-Mbit DDR-II SRAM)
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