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參數(shù)資料
| 型號： | CY7C1316BV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit DDR-II SRAM 2-Word Burst Architecture(2字Burst結構,18-Mbit DDR-II SRAM) |
| 中文描述： | 18兆位的DDR - II SRAM的2字突發(fā)架構（2字突發(fā)結構,18 -兆位的DDR - II SRAM的） |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 469K |
| 代理商： | CY7C1316BV18 |
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CY7C1316BV18
CY7C1916BV18
CY7C1318BV18
CY7C1320BV18
Document Number: 38-05621 Rev. *C
Page 22 of 28
Switching Characteristics
Over the Operating Range
[22,23]
Cypress
Parameter
t
POWER
Consortium
Parameter
t
KHKH
Description
300 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1
–
1
–
1
278 MHz
250 MHz
200 MHz
167 MHz
Unit
ms
V
DD
(Typical) to the first
Access
[24]
1
1
t
CYC
t
KHKL
K Clock and C Clock Cycle
Time
Input Clock (K/K and C/C)
HIGH
Input Clock (K/K and C/C)
LOW
K Clock Rise to K Clock
Rise and C to C Rise (rising
edge to rising edge)
K/K Clock Rise to C/C Clock
Rise (rising edge to rising edge)
3.30
5.25
3.60
5.25
4.0
6.3
5.0
7.9
6.0
8.4
ns
t
KH
t
KLKH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KL
t
KHKH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KHKH
t
KHCH
1.49
–
1.6
–
1.8
–
2.2
–
2.7
–
ns
t
KHCH
t
KHKH
0.00
1.45
0.00
1.55
0.0
1.8
0.0
2.2
0.0
2.7
ns
Set-up Times
t
SA
t
AVKH
Address Set-up to K Clock
Rise
Control Set-up to K Clock
Rise (LD, R/W)
Double Data Rate Control
Set-up to Clock (K, K) Rise
(BWS
0
, BWS
1
, BWS
2
,
BWS
3
)
D
[X:0]
Set-up to Clock
(K/K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SC
t
IVKH
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SCDDR
t
IVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
SD[25]
t
DVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after K Clock
Rise
Control Hold after K Clock
Rise (LD, R/W)
Double Data Rate Control
Hold after Clock (K, K) Rise
(BWS
0
, BWS
1
, BWS
2
,
BWS
3
)
D
[X:0]
Hold after Clock
(K and K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HC
t
KHIX
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HCDDR
t
KHIX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
HD
t
KHDX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in
single clock mode) to Data
Valid
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
Notes:
23.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
24.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
25.For DQ2 data signal on CY7C1916BV18 device, t
SD
is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.
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| CY7C1318BV18-167BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V COM DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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