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參數(shù)資料
| 型號： | CY7C1316AV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 18兆位的DDR - II SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 228K |
| 代理商： | CY7C1316AV18 |
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 9 of 20
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +2.9V
DC Applied to Outputs in High-Z......... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage
[9]
.............................. –0.5V to V
DDQ
+ 0.5V
Electrical Characteristics
Over the Operating Range
[11]
DC Electrical Characteristics
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V
Latch-up Current..................................................... >200 mA
Operating Range
Range
Com’l
Ambient
Temperature
0°C to +70°C
V
DD
[10]
1.8 ± 0.1V
V
DDQ
[10]
1.4V to V
DD
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
OH(LOW)
V
OL(LOW)
V
IH
V
IL
V
IN
I
X
I
OZ
V
REF
I
DD
Description
Test Conditions
Min.
1.7
1.4
Typ.
1.8
1.5
Max.
1.9
V
DD
Unit
V
V
V
V
V
V
V
V
V
μ
A
μ
A
V
mA
mA
mA
mA
mA
mA
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
[9]
Input LOW Voltage
[9, 14]
Clock Input Voltage
Input Load Current
Output Leakage Current
Input Reference Voltage
[15]
V
DD
Operating Supply
Note 12
Note 13
I
OH
= –0.1 mA, Nominal Impedance
I
OL
= 0.1 mA, Nominal Impedance
V
DDQ
/2 – 0.12
V
DDQ
/2 – 0.12
V
DDQ
– 0.2
V
SS
V
REF
+ 0.1
–0.3
–0.3
–5
–5
0.68
V
DDQ
/2 + 0.12
V
DDQ
/2 + 0.12
V
DDQ
0.2
V
DDQ
+ 0.3
V
REF
– 0.1
V
DD
+ 0.3
5
5
0.95
700
750
800
450
470
490
GND
≤
V
I
≤
V
DDQ
GND
≤
V
I
≤
V
DDQ,
Output Disabled
Typical Value = 0.75V
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
0.75
167 MHz
200 MHz
250 MHz
167 MHz
200 MHz
250 MHz
I
SB1
Automatic Power-down
Current
Max. V
DD
, Both Ports
Deselected, V
IN
≥
V
IH
or
V
IN
≤
V
IL
f = f
MAX
=
1/t
CYC
, Inputs Static
AC Input Requirements
Parameter
V
IH
Input High (Logic 1) Voltage
V
IL
Input Low (Logic 0) Voltage
Capacitance
[16]
Description
Test Conditions
Min.
Typ.
–
–
Max.
–
Unit
V
V
V
REF
+ 0.2
–
V
REF
– 0.2
Parameter
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 1.8V
V
DDQ
= 1.5V
Max.
5
6
7
Unit
pF
pF
pF
C
IN
C
CLK
C
O
Notes:
9. Overshoot: V
(AC) < V
+0.85V (Pulse width less than t
/2); Undershoot V
(AC) >
1.5V (Pulse width less than t
TCYC
/2).
10.Power-up: Assumes a linear ramp from 0V to V
DD
(Min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
11. All voltage referenced to ground.
12.Outputs are impedance controlled. I
OH
= –(V
DDQ
/2)/(RQ/5) for values of 175
< RQ < 350
.
13.Outputs are impedance controlled. I
= (V
/2)/(RQ/5) for values of 175
< RQ < 350
.
14.This spec is for all inputs except C and C Clock. For C and C Clock, V
(Max.) = V
– 0.2V.
15.V
(Min.) = 0.68V or 0.46V
, whichever is larger, V
(Max.) = 0.95V or 0.54V
, whichever is smaller.
16.Tested initially and after any design or process change that may affect these parameters.
Input Capacitance
Clock Input Capacitance
Output Capacitance
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