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參數(shù)資料
| 型號(hào)： | CY7C1316AV18 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 18兆位的DDR - II SRAM的2字突發(fā)結(jié)構(gòu) |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 228K |
| 代理商： | CY7C1316AV18 |
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 8 of 20
Write Cycle Descriptions
(CY7C1316AV18 and CY7C1318AV18)
[2, 8]
BWS
0
BWS
1
L
K
K
–
Comments
L
L-H
During the Data portion of a Write sequence
:
CY7C1316AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1318AV18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1316AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1318AV18
both bytes (D
[17:0]
) are written into the device.
–
During the Data portion of a Write sequence
:
CY7C1316AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1318AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
L-H During the Data portion of a Write sequence
:
CY7C1316AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1318AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
–
During the Data portion of a Write sequence
:
CY7C1316AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1318AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
L-H During the Data portion of a Write sequence
:
CY7C1316AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1318AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
L
L
–
L
H
L-H
L
H
–
H
L
L-H
H
L
–
H
H
H
H
L-H
–
Write Cycle Descriptions
[2, 8]
(CY7C1320AV18)
BWS
0
L
BWS
1
L
BWS
2
L
BWS
3
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is
written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L
L
L
L
–
L-H
L
H
H
H
L-H
–
L
H
H
H
–
L-H
H
L
H
H
L-H
–
H
L
H
H
–
L-H
H
H
L
H
L-H
–
H
H
L
H
–
L-H
H
H
H
L
L-H
H
H
H
L
–
L-H
H
H
H
H
H
H
H
H
L-H
–
–
L-H
Note:
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
, BWS
in the case of CY7C1316AV18 and CY7C1318AV18 and
also BWS
2
, BWS
3
in the case of CY7C1320AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1316AV18-167BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1318AV18-200BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1318AV18-250BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320AV18-167BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1316AV18-200BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C13181SC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C13181XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1318AV18-167BZC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C1318AV-200BZCES | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1318BV18-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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