參數(shù)資料
型號(hào)： CY7C1316AV18
廠(chǎng)商： Cypress Semiconductor Corp.
元件分類(lèi)： DRAM
英文描述： 18-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述： 18兆位的DDR - II SRAM的2字突發(fā)結(jié)構(gòu)
文件頁(yè)數(shù)： 10/20頁(yè)
文件大?。?/td> 228K
代理商： CY7C1316AV18
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 10 of 20
AC Test Loads and Waveforms
Thermal Resistance
[16]
Parameter
Θ
JA
Θ
JC
Description
Test Conditions
165 FBGA Package
16.7
2.5
Unit
°
C/W
°
C/W
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
Thermal Resistance (Junction to Case)
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
Switching Characteristics
Over the Operating Range
[17,18]
Cypress
Parameter
t
CYC
t
KH
t
KL
t
KHKH
Consortium
Parameter
t
KHKH
t
KHKL
t
KLKH
t
KHKH
Description
250 MHz
Min. Max. Min. Max.
4.0
6.3
1.6
–
1.6
–
1.8
–
200 MHz
167 MHz
Min.
6.0
2.4
2.4
2.7
Unit
ns
ns
ns
ns
Max.
8.4
–
–
–
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K Clock Rise to K Clock Rise and C to C Rise (rising
edge to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) 0.0
5.0
2.0
2.0
2.2
7.9
–
–
–
t
KHCH
Set-up Times
t
SA
t
SC
t
SCDDR
t
KHCH
1.8
0.0
2.3
0.0
2.8
ns
t
SA
t
SC
t
SC
Address Set-up to K Clock Rise
Control Set-up to Clock (K, K) Rise (LD, R/W)
Double Data Rate Control Set-up to Clock (K, K)
Rise (BWS
0
, BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Set-up to Clock (K and K) Rise
0.5
0.5
0.35
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
t
SD
Hold Times
t
HA
t
HC
t
HCDDR
t
SD
0.35
–
0.4
–
0.5
–
ns
t
HA
t
HC
t
HC
Address Hold after Clock (K and K) Rise
Control Hold after Clock (K and K) Rise (LD, R/W)
Double Data Rate Control Hold after Clock (K and
K) Rise (BWS
0
, BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Hold after Clock (K and K) Rise
0.5
0.5
0.35
–
–
–
0.6
0.6
0.4
–
–
–
0.7
0.7
0.5
–
–
–
ns
ns
ns
t
HD
Output Times
t
CO
t
DOH
t
HD
0.35
–
0.4
–
0.5
–
ns
t
CHQV
t
CHQX
C/C Clock Rise (or K/K in single clock mode) to Data Valid
Data Output Hold after Output C/C Clock Rise
(Active to Active)
C/C Clock Rise to Echo Clock Valid
–
0.45
–
–
0.45
–
–
0.50
–
ns
ns
–0.45
–0.45
–0.50
t
CCQO
Notes:
17.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
18.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250
, V
DDQ
= 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified I
OL
/I
OH
and load capacitance shown in (a) of AC Test Loads.
t
CHCQV
–
0.45
–
0.45
–
0.50
ns
1.25V
0.25V
R = 50
5 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device
Under
Test
R
L
= 50
Z
0
= 50
V
REF
= 0.75V
V
REF
= 0.75V
[15]
0.75V
0.75V
Device
Under
Test
OUTPUT
0.75V
V
REF
V
REF
OUTPUT
ZQ
ZQ
(a)
RQ =
250
(b)
RQ =
250
Slew Rate = 2V/ns
相關(guān)PDF資料
PDF描述
CY7C1316AV18-167BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1318AV18-200BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1318AV18-250BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320AV18-167BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316AV18-200BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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CY7C1318AV18-167BZC 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:
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CY7C1318BV18-167BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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