參數(shù)資料
型號(hào): CY7C1316AV18
廠商: Cypress Semiconductor Corp.
元件分類: DRAM
英文描述: 18-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述: 18兆位的DDR - II SRAM的2字突發(fā)結(jié)構(gòu)
文件頁數(shù): 15/20頁
文件大?。?/td> 228K
代理商: CY7C1316AV18
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 15 of 20
TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range
[9, 11, 25]
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Description
Test Conditions
I
OH
=
2.0 mA
I
OH
=
100
μ
A
I
OL
= 2.0 mA
I
OL
= 100
μ
A
Min.
1.4
1.6
Max.
Unit
V
V
V
V
V
V
μ
A
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and OutputLoad Current
0.4
0.2
0.65V
DD
–0.3
5
V
DD
+ 0.3
0.35V
DD
5
GND
V
I
V
DD
TAP AC Switching Characteristics
Over the Operating Range
[26, 27]
Parameter
t
TCYC
t
TF
t
TH
t
TL
Notes:
25.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
26.t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
27.Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
Description
Min.
100
Max.
Unit
ns
MHz
ns
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
10
40
40
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
106
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
相關(guān)PDF資料
PDF描述
CY7C1316AV18-167BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1318AV18-200BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1318AV18-250BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320AV18-167BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1316AV18-200BZC 18-Mbit DDR-II SRAM 2-Word Burst Architecture
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