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參數(shù)資料
| 型號(hào)： | CY7C1316AV18-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 8 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 228K |
| 代理商： | CY7C1316AV18-167BZC |
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 5 of 20
R/W
Input-
Synchronous
Synchronous Read/Write Input
. When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
Positive Output Clock Input
. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Negative Output Clock Input
. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Positive Input Clock Input
. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated
on the rising edge of K.
Negative Input Clock Input
. K is used to capture synchronous data being presented to the device
and to drive out data through Q
[x:0]
when in single clock mode.
CQ is referenced with respect to C
. This is a free-running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
CQ is referenced with respect to C
. This is a free-running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Output Impedance Matching Input
. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2
×
RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V
DD
,
which enables the minimum impedance mode. This pin cannot be connected directly to GND or
left unconnected.
DLL Turn Off—active LOW
. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note, “DLL Operation in the
QDR-II.”
TDO for JTAG
.
TCK pin for JTAG
.
TDI pin for JTAG
.
TMS pin for JTAG
.
Not connected to the die
. Can be tied to any voltage level.
Address expansion for 36M
. This is not connected to the die and so can be tied to any voltage
level.
Address expansion for 72M
. This is not connected to the die and so can be tied to any voltage
level.
Address expansion for 72M
. This must be tied LOW.
Address expansion for 144M
. This must be tied LOW.
Address expansion for 288M
. This must be tied LOW.
Reference Voltage Input
. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
Power Supply
Power supply inputs to the core of the device
.
Ground
Ground for the device
.
Power Supply
Power supply inputs for the outputs of the device
.
C
Input-
Clock
C
Input-
Clock
K
Input-
Clock
K
Input-
Clock
Output-
Clock
CQ
CQ
Output-
Clock
ZQ
Input
DOFF
Input
TDO
TCK
TDI
TMS
NC
NC/36M
Output
Input
Input
Input
N/A
N/A
NC/72M
N/A
V
SS
/72M
V
SS
/144M
V
SS
/288M
V
REF
Input
Input
Input
Input-
Reference
V
DD
V
SS
V
DDQ
Pin Definitions
(continued)
Pin Name
I/O
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1318AV18-200BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1318AV18-250BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320AV18-167BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1316AV18-200BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320AV18-200BZC | IC MUX/DEMUX DIFF 42-TQFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C13181SC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C13181XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1318AV18-167BZC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C1318AV-200BZCES | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1318BV18-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 1.8V COM DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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