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參數(shù)資料
| 型號： | CY7C1316AV18-167BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 8 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 228K |
| 代理商： | CY7C1316AV18-167BZC |
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 11 of 20
t
CQOH
t
CQD
t
CQDOH
t
CHZ
t
CLZ
DLL Timing
t
KC Var
t
KC lock
t
KC Reset
t
CHCQX
t
CQHQV
t
CQHQX
t
CHZ
t
CLZ
Echo Clock Hold after C/C Clock Rise
–0.45
–
–0.45
–
–0.50
–
ns
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Clock (C and C) Rise to High-Z (Active to High-Z)
[19, 20]
Clock (C and C) Rise to Low-Z
[19, 20]
–
0.30
–
0.45
–
–
0.35
–
0.45
–
–
0.40
–
0.50
–
ns
ns
ns
ns
–0.30
–
–0.45
–0.35
–
–0.45
–0.40
–
–0.50
t
KC Var
t
KC lock
t
KC Reset
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
–
0.20
–
–
0.20
–
–
0.20
–
ns
1024
30
1024
30
1024
30
Cycles
ns
Switching Characteristics
Over the Operating Range (continued)
[17,18]
Cypress
Parameter
Consortium
Parameter
Description
250 MHz
Min. Max. Min. Max.
200 MHz
167 MHz
Min.
Unit
Max.
Switching Waveforms
[21, 22, 23]
Notes:
19.t
, t
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
100 mV from steady-state voltage.
20.At any given voltage and temperature t
is less than t
and t
less than t
.
21.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
22.Output are disabled (High-Z) one clock cycle after a NOP.
23.In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
K
1
2
3
4
5
6
7
8
9
10
K
LD
R/W
A
DQ
C
C#
READ
READ
READ
NOP
NOP
WRITE
WRITE
Q40
tKH
tKHKH
tKHCH
tCO
tKL
tCYC
t
tHC
tSA
tHA
tSD
tHD
tKHCH
NOP
tSD
tHD
DON’T CARE
UNDEFINED
tCLZ
tDOH
tCHZ
tDOH
SC
tKH
tKHKH
tKL
tCYC
A0
D20
D21
D30
D31
Q00
Q11
Q01
Q10
Qx2
tCO
tCQD
A1
A2
A3
A4
Q41
CQ
CQ#
tCCQO
tCQOH
tCCQO
tCQOH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1318AV18-200BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1318AV18-250BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320AV18-167BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1316AV18-200BZC | 18-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1320AV18-200BZC | IC MUX/DEMUX DIFF 42-TQFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C13181SC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C13181XC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1318AV18-167BZC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C1318AV-200BZCES | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1318BV18-167BZC | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 1.8V COM DDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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