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參數(shù)資料
| 型號： | CY7C1176V18-300BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 2M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 956K |
| 代理商： | CY7C1176V18-300BZXI |
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CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 18 of 29
Identification Register Definitions
Instruction Field
Value
Description
CY7C1161V18
000
CY7C1176V18
000
CY7C1163V18
000
CY7C1165V18
000
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC ID
(11:1)
Version number.
11010010001000101 11010010001001101 11010010001010101 11010010001100101 Defines the type of
SRAM.
Enables unique
identification of
SRAM vendor.
Indicates the
presence of an ID
register.
00000110100
00000110100
00000110100
00000110100
ID Register
Presence (0)
1
1
1
1
Scan Register Sizes
Register Name
Bit Size
3
1
32
107
Instruction
Bypass
ID
Boundary Scan
Instruction Codes
Instruction
Code
000
001
Description
EXTEST
IDCODE
Captures the input and output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the input and output contents. Places the boundary scan register between
TDI and TDO. This forces all SRAM output drivers to a High Z state.
Do Not Use: This instruction is reserved for future use.
Captures the input and output ring contents. Places the boundary scan register
between TDI and TDO. This operation does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1176V18-333BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1166V18 | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1214F-100ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215F-166AC | 制造商:Rochester Electronics LLC 功能描述:1MB (32K X 32) 3.3V PIPELINE SCD - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
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