參數(shù)資料
型號(hào)： CY7C1176V18-300BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述： 2M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FPBGA-165
文件頁(yè)數(shù)： 12/29頁(yè)
文件大?。?/td> 956K
代理商： CY7C1176V18-300BZXI
CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 12 of 29
The write cycle descriptions of CY7C1165V18 follows.
[3, 11]
BWS
0
BWS
1
BWS
2
BWS
3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D
[35:0]
) are written into
the device.
L
L
L
L
–
L–H During the data portion of a write sequence, all four bytes (D
[35:0]
) are written into
the device.
L
H
H
H
L–H
–
During thedata portion of a write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
remains unaltered.
L
H
H
H
–
L–H During the data portion of a write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
remains unaltered.
H
L
H
H
L–H
–
During the data portion of a write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
remains unaltered.
H
L
H
H
–
L–H During the data portion of a write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
remains unaltered.
H
H
L
H
L–H
–
During the data portion of a write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
remains unaltered.
H
H
L
H
–
L–H During the data portion of a write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
remains unaltered.
H
H
H
L
L–H
–
During the data portion of a write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
remains unaltered.
H
H
H
L
–
L–H During the data portion of a write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
remains unaltered.
H
H
H
H
L–H
–
No data is written into the device during this portion of a write operation.
H
H
H
H
–
L–H No data is written into the device during this portion of a write operation.
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相關(guān)PDF資料
PDF描述
CY7C1176V18-333BZC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZXC 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1176V18-333BZXI 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1166V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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