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參數資料
| 型號： | CY7C1176V18-300BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 2M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165 |
| 文件頁數： | 25/29頁 |
| 文件大?。?/td> | 956K |
| 代理商： | CY7C1176V18-300BZC |
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CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 25 of 29
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency
[30, 31, 32]
tKH
tKL
tCYC
tKHKH
t
t
t
tSA
HA
SC
HC
tHD
tSC
tHC
A0
A1
A2
A3
t
t
SD
HD
tSD
D11
D10
D12
D13
D30
D31
D32
D33
t
QVLD
D
A
WPS
RPS
K
K
NOP
6
READ
2
NOP
1
WRITE
3
READ
4
WRITE
5
7
8
CQ
CQ
Q
tCQOH
CCQO
t
CLZ
t
t
CO
tDOH
tCQDOH
CQD
t
tCHZ
tCQOH
CCQO
t
tQVLD
QVLD
DON’T CARE
UNDEFINED
(Read Latency = 2.5 Cycles)
Q00
Q01
Q20
Q02
Q21
Q03
Q22
Q23
tCQH
t
CQHCQH
Notes
30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
31.Outputs are disabled (High Z) one clock cycle after a NOP.
32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
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相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1176V18-300BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-300BZXC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-300BZXI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZC | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| CY7C1176V18-333BZI | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
相關代理商/技術參數 |
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| CY7C1214F-100AC | 制造商:Cypress Semiconductor 功能描述: |
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