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參數(shù)資料
| 型號： | CY7C1176V18-300BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
| 中文描述： | 2M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165 |
| 文件頁數(shù)： | 23/29頁 |
| 文件大?。?/td> | 956K |
| 代理商： | CY7C1176V18-300BZC |
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CY7C1161V18
CY7C1176V18
CY7C1163V18
CY7C1165V18
Document Number: 001-06582 Rev. *C
Page 23 of 29
Switching Characteristics
Over the operating range
[22, 23]
Cypress
Parameter
Consortium
Parameter
Description
400 MHz
375 MHz
333 MHz
300 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
t
POWER
t
CYC
t
KH
t
KL
t
KHKH
V
DD
(Typical) to the First Access
[24]
K Clock Cycle Time
1
–
1
–
1
–
1
–
ms
t
KHKH
t
KHKL
t
KLKH
t
KHKH
2.50 8.40 2.66 8.40
3.0
8.40
3.3
8.40
ns
Input Clock (K/K) HIGH
0.4
–
0.4
–
0.4
–
0.4
–
t
CYC
t
CYC
ns
Input Clock (K/K) LOW
0.4
–
0.4
–
0.4
–
0.4
–
K Clock Rise to K Clock Rise
(rising edge to rising edge)
1.06
–
1.13
–
1.28
–
1.40
–
Setup Times
t
SA
t
SC
t
SCDDR
t
AVKH
t
IVKH
t
IVKH
Address Setup to K Clock Rise
0.4
–
0.4
–
0.4
–
0.4
–
ns
Control Setup to K Clock Rise (RPS, WPS)
0.4
–
0.4
–
0.4
–
0.4
–
ns
Double Data Rate Control Setup to Clock (K, K)
Rise (BWS
0
, BWS
1,
BWS
2
, BWS
3
)
D
[X:0]
Setup to Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
0.28
–
ns
t
SD
Hold Times
t
DVKH
0.28
–
0.28
–
0.28
–
0.28
–
ns
t
HA
t
HC
t
HCDDR
t
KHAX
t
KHIX
t
KHIX
Address Hold after K Clock Rise
0.4
–
0.4
–
0.4
–
0.4
–
ns
Control Hold after K Clock Rise (RPS, WPS)
0.4
–
0.4
–
0.4
–
0.4
–
ns
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS
0
, BWS
1,
BWS
2
, BWS
3
)
D
[X:0]
Hold after Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
0.28
–
ns
t
HD
Output Times
t
KHDX
0.28
–
0.28
–
0.28
–
0.28
–
ns
t
CO
t
DOH
t
CHQV
t
CHQX
K/K Clock Rise to Data Valid
–
0.45
–
0.45
–
0.45
–
0.45
ns
Data Output Hold after Output K/K Clock Rise
(Active to Active)
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
t
CCQO
t
CQOH
t
CQD
t
CQDOH
t
CQH
t
CQHCQH
t
CHCQV
t
CHCQX
t
CQHQV
t
CQHQX
t
CQHCQL
t
CQHCQH
K/K Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
ns
Echo Clock Hold after K/K Clock Rise
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
Echo Clock High to Data Valid
–
0.2
0.2
0.2
0.2
ns
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH
[25]
CQ Clock Rise to CQ Clock Rise
[25]
(rising edge to rising edge)
Clock (K/K) Rise to High Z (Active to High Z)
[26, 27]
Clock (K/K) Rise to Low Z
[26, 27]
Echo Clock High to QVLD Valid
[28]
–0.2
–
–0.2
–
–0.2
–
–0.2
–
ns
0.81
–
0.88
–
1.03
–
1.15
–
ns
0.81
–
0.88
–
1.03
–
1.15
–
ns
t
CHZ
t
CLZ
t
QVLD
t
CHQZ
t
CHQX1
t
QVLD
–
0.45
–
0.45
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
–0.45
–
–0.45
–
ns
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20
ns
Notes
23.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
24.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a Read or Write operation can
be initiated.
25.These parameters are extrapolated from the input timing parameters (t
KHKH
– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
KC Var
) is already
included in the t
KHKH
). These parameters are only guaranteed by design and are not tested in production.
26.t
CHZ
, t
CLZ
are specified with a load capacitance of 5 pF as in part (b) of
AC Test Loads and Waveforms
. Transition is measured
±
100 mV from steady state voltage.
27.At any given voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
28.t
QVLD
spec is applicable for both rising and falling edges of QVLD signal.
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