參數(shù)資料
型號: CY7C1049BNV33-12VI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 512K x 8 Static RAM
中文描述: 512K X 8 STANDARD SRAM, 12 ns, PDSO36
封裝: 0.400 INCH, SOJ-36
文件頁數(shù): 4/8頁
文件大?。?/td> 420K
代理商: CY7C1049BNV33-12VI
CY7C1049BNV33
Document #: 001-06432 Rev. **
Page 4 of 8
Data Retention Characteristics
Over the Operating Range (For L version only)
Parameter
Description
Conditions
[10]
Min.
2.0
Max
Unit
V
μ
A
ns
V
DR
I
CCDR
t
CDR[3]
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
330
0
t
R[11]
t
RC
ns
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1
[12, 13]
Read Cycle No. 2 (OE Controlled)
[13, 14]
Notes:
12.Device is continuously selected. OE, CE = V
IL
.
13.WE is HIGH for read cycle.
14.Address valid prior to or coincident with CE transition LOW.
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
CC
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
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