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參數(shù)資料
| 型號(hào)： | CY7C1049BNV33-12VI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 12 ns, PDSO36 |
| 封裝： | 0.400 INCH, SOJ-36 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 420K |
| 代理商： | CY7C1049BNV33-12VI |
CY7C1049BNV33
Document #: 001-06432 Rev. **
Page 3 of 8
AC Test Loads and Waveforms
AC Switching Characteristics
[4]
Over the Operating Range
-12
-15
-20
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. T.
power
time has to be provided initially before a read/write operation is
started.
6. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
7. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
10.No input may exceed V
+ 0.5V
11. .t
r
< 3 ns for the -12 and -15 speeds. t
r
< 5 ns for the -20 ns and slower speeds.
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
CC
(typical) to the First Access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
1
1
1
20
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
12
15
12
15
20
3
3
3
12
6
15
7
20
8
0
0
0
6
7
8
3
3
3
6
7
8
ns
ns
ns
0
0
0
12
15
20
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
12
10
10
0
0
10
7
0
3
15
12
12
0
0
12
8
0
3
20
13
13
0
0
13
9
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
7
8
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
OUTPUT
(a)
(b)
R1 317
167
R2
351
VENIN EQUIVALENT
THé
1.73V
RiseTime:1 V/ns
Fall time:
1 V/ns
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1049BNV33-12VXC | 512K x 8 Static RAM |
| CY7C1049BNV33-12VXI | 512K x 8 Static RAM |
| CY7C1049BNV33-12ZC | 512K x 8 Static RAM |
| CY7C1049BNV33-15VC | 512K x 8 Static RAM |
| CY7C1049BNV33-15VI | 512K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1049BNV33-12VXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1049BNV33-15VXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1049BNV33-15ZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1049BNV33-15ZI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1049BNV33L-15VXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
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