參數(shù)資料
型號(hào)： CY7C09569V
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x 36 FLEx36 Synchronous Dual-Port Static RAM(3.3V 16K x 36 同步雙端口靜態(tài) RAM)
中文描述： 3.3 16K的× 36 FLEx36同步雙端口靜態(tài)RAM（3.3 16K的× 36同步雙端口靜態(tài)RAM）的
文件頁(yè)數(shù)： 5/30頁(yè)
文件大小： 1059K
代理商： CY7C09569V
CY7C09569V
CY7C09579V
Document #: 38-06054 Rev. *B
Page 5 of 30
Selection Guide
CY7C09569V
CY7C09579V
-100
100
5
250
30
10
CY7C09569V
CY7C09579V
-83
83
6
240
25
10
CY7C09569V
CY7C09579V
-67
67
8
230
25
10
Unit
MHz
ns
mA
mA
μ
A
f
MAX2
(Pipelined)
Max. Access Time (Clock to Data, Pipelined)
Typical Operating Current I
CC
Typical Standby Current for I
SB1
(Both Ports TTL Level)
Typical Standby Current for I
SB3
(Both Ports CMOS Level)
Pin Definitions
Left Port
A
0L
–A
13/14L
ADS
L
Right Port
A
0R
–A
13/14R
ADS
R
Description
Address Inputs (A
0
–A
13
for 16K, A
0
–A
14
for 32K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
assert the part using the externally supplied address on Address Pins. To load this address into
the Burst Address Counter both ADS and CNTEN have to be LOW. ADS is disabled if CNTRST
is asserted LOW
Chip Enable Input.
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if CNTRST is asserted LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output.
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
Byte Select Inputs. Asserting these signals enable read and write operations to the corre-
sponding bytes of the memory array.
CE
L
CLK
L
CNTEN
L
CE
R
CLK
R
CNTEN
R
CNTRST
L
CNTRST
R
I/O
0L
–I/O
35L
OE
L
I/O
0R
–I/O
35R
OE
R
R/W
L
R/W
R
FT/PIPE
L
FT/PIPE
R
B
0L
–B
3L
BM, SIZE
Select Pins for Bus Matching. See Bus Matching for details.
BE
Big Endian Pin. See Bus Matching for details.
V
SS
V
DD
Ground Input.
Power Input.
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參數(shù)描述
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CY7C09569V83AC 制造商:Cypress Semiconductor 功能描述:
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