參數(shù)資料
型號(hào): CY7C09569V
廠商: Cypress Semiconductor Corp.
英文描述: 3.3V 16K x 36 FLEx36 Synchronous Dual-Port Static RAM(3.3V 16K x 36 同步雙端口靜態(tài) RAM)
中文描述: 3.3 16K的× 36 FLEx36同步雙端口靜態(tài)RAM(3.3 16K的× 36同步雙端口靜態(tài)RAM)的
文件頁(yè)數(shù): 11/30頁(yè)
文件大?。?/td> 1059K
代理商: CY7C09569V
CY7C09569V
CY7C09579V
Document #: 38-06054 Rev. *B
Page 11 of 30
Bus Match Read Cycle for Flow-Through Output (FT/PIPE = V
IL
)
[10, 12, 14, 15, 16]
Bus Match Read Cycle for Pipelined Operation (FT/PIPE = V
IH
)
[10, 12, 14, 15, 16]
Notes:
14.Timing shown is for x18 bus matching; x9 bus matching is similar with 4 cycles between address inputs.
15.See table “Right Port Operation“ for data output on first and subsequent cycles.
16.CNTEN = V
. In x9 and x18 Bus Matching Burst Mode operations (Write or Read), ADS can toggle on the rising edge of every clock cycle or it can be at V
IH
level
all the time except when loading the initial external address (i.e. ADS = V
IL
only required when reading or writing the first Byte or Word).
Switching Waveforms
(continued)
t
CH1
t
CL1
t
CYC1
t
DC
t
SC
t
HC
t
SW
t
SA
t
HW
t
HA
t
DC
t
CKLZ
A
n
A
n
A
n+1
A
n+1
Q
n
1st
Cycle
Q
n
Q
n+1
1st
Cycle
CLK
CE
R/W
ADDRESS
DATA
OUT
OE
LOW
Q
n+1
2nd
Cycle
2nd
Cycle
t
CD1
ADS
t
CH2
CLK
CE
R/W
ADDRESS
DATA
OUT
OE
A
n
A
n
A
n+1
A
n+1
Q
n
Q
n+1
Q
n
t
CYC2
t
CL2
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
1 Latency
t
CD2
t
CLKZ
LOW
1st Cycle
2nd Cycle
1st Cycle
t
CD2
t
CD2
t
DC
t
DC
t
DC
ADS
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