參數(shù)資料
型號(hào)： CY7C09569V
廠商： Cypress Semiconductor Corp.
英文描述： 3.3V 16K x 36 FLEx36 Synchronous Dual-Port Static RAM(3.3V 16K x 36 同步雙端口靜態(tài) RAM)
中文描述： 3.3 16K的× 36 FLEx36同步雙端口靜態(tài)RAM（3.3 16K的× 36同步雙端口靜態(tài)RAM）的
文件頁(yè)數(shù)： 26/30頁(yè)
文件大小： 1059K
代理商： CY7C09569V
CY7C09569V
CY7C09579V
Document #: 38-06054 Rev. *B
Page 26 of 30
Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O
0R–17R
. The level applied to the Big Endian (BE) pin
determines the right port data I/O sequencing order (Big
Endian or Little Endian).
During word (18-bit) bus size operation, a logic LOW applied
to the BE pin will select Little Endian operation. In this case,
the least significant data word is read from the right port first
or written to the right port first. A logic “1” on the BE pin during
word (18-bit) bus size operation will select Big Endian
operation resulting in the most significant data word being
transferred through the right port first. Internally, the data will
be stored in the appropriate 36-bit LSB or MSB I/O memory
location. Device operation requires a minimum of two clock
cycles to read or write during word (18-bit) bus size operation.
An internal sub-counter automatically increments the right port
multiplexer control when Little or Big Endian operation is in
effect.
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “1.” In this mode, 9 bits of data are ported
through I/O
0R–8R
.
Big Endian and Little Endian data sequencing is available for
dual-port operation. The level applied to the Big Endian pin
(BE) under these circumstances will determine the right port
data I/O sequencing order (Big or Little Endian). A logic LOW
applied to the BE pin during byte (9-bit) bus size operation will
select Little Endian operation. In this case, the least significant
data byte is read from the right port first or written to the right
port first. A logic “1” on the BE pin during byte (9-bit) bus size
operation will select Big Endian operation resulting in the most
significant data word to be transferred through the right port
first. Internally, the data will be stored in the appropriate 36-bit
LSB or MSB I/O memory location. Device operation requires
a minimum of four clock cycles to read or write during byte (9-
bit) bus size operation. An internal sub-counter automatically
increments the right port multiplexer control when Little or Big
Endian operation is in effect. When transferring data in byte (9-
bit) bus match format, the unused I/O pins (I/O
9RQ–35R
) are
three-stated.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C09569V-100AC 功能描述:IC SRAM 576KBIT 100MHZ 144LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR)
CY7C09569V-100AXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512K (16Kx36) 3.3v 100MHz Synch 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C09569V-100BBC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512K (16Kx36) 3.3v 100MHz Synch 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C09569V-67AC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 576K-Bit 16K x 36 20ns/8ns 144-Pin TQFP
CY7C09569V83AC 制造商:Cypress Semiconductor 功能描述:
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