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參數(shù)資料
| 型號： | CY7C0852V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| 中文描述： | FLEx36TM 3.3 32K/64K/128K/256K × 36同步雙口RAM |
| 文件頁數(shù)： | 6/29頁 |
| 文件大?。?/td> | 764K |
| 代理商： | CY7C0852V |
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CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 6 of 29
Pin Definitions
Note:
3.
These pins are not available for CY7C0853V device.
Left Port
A
0L
–A
17L[1]
Right Port
A
0R
–A
17R[1]
Description
Address Inputs
.
Address Strobe Input
. Used as an address qualifier. This signal should be asserted LOW
for the part using the externally supplied address on the address pins and for loading this
address into the burst address counter.
ADS
L[3]
ADS
R[3]
CE0
L[3]
CE1
L[3]
CLK
L
CE0
R[3]
CE1
R[3]
CLK
R
Active LOW Chip Enable Input
.
Active HIGH Chip Enable Input
.
Clock Signal
. Maximum clock input rate is f
MAX
.
Counter Enable Input
.
Asserting this signal LOW increments the burst address counter of
its respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST
are asserted LOW.
Counter Reset Input
. Asserting this signal LOW resets to zero the unmasked portion of
the burst address counter of its respective port. CNTRST is not disabled by asserting ADS
or CNTEN.
A
ddress Counter Mask Register Enable Input
. Asserting this signal LOW enables access
to the mask register. When tied HIGH, the mask register is not accessible and the address
counter operations are enabled based on the status of the counter control signals.
Data Bus Input/Output
.
Output Enable Input
. This asynchronous signal must be asserted LOW to enable the DQ
data pins during Read operations.
Mailbox Interrupt Flag Output
.
The mailbox permits communications between ports. The
upper two memory locations can be used for message passing. INT
L
is asserted LOW when
the right port writes to the mailbox location of the left port, and vice versa. An interrupt to a
port is deasserted HIGH when it reads the contents of its mailbox.
Counter Interrupt Output
. This pin is asserted LOW when the unmasked portion of the
counter is incremented to all “1s.”
Read/Write Enable Input
. Assert this pin LOW to write to, or HIGH to Read from the dual
port memory array.
Byte Select Inputs
. Asserting these signals enables Read and Write operations to the
corresponding bytes of the memory array.
Master Reset Input
. MRST is an asynchronous input signal and affects both ports.
Asserting MRST LOW performs all of the reset functions as described in the text. A MRST
operation is required at power-up.
JTAG Test Mode Select Input
. It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
JTAG Test Data Input
. Data on the TDI input will be shifted serially into selected registers.
JTAG Test Clock Input
.
JTAG Test Data Output
. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs
.
Power Inputs
.
CNTEN
L[3]
CNTEN
R[3]
CNTRST
L[3]
CNTRST
R[3]
CNT/MSK
L[3]
CNT/MSK
R[3]
DQ
0L
–DQ
35L
DQ
0R
–DQ
35R
OE
L
OE
R
INT
L
INT
R
CNTINT
L[3]
CNTINT
R[3]
R/W
L
R/W
R
B
0L
–B
3L
B
0R
–B
3R
MRST
TMS
TDI
TCK
TDO
V
SS
V
DD
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C0850V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-133AC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-133AI | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-133BBC | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0850V-133BBI | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0852V-100BBC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 128KX36 5NS 172BGA - Bulk |
| CY7C0852V-133AC | 制造商:Rochester Electronics LLC 功能描述:3.3V 128KX36 SYNC DUAL PORT SRAM - Bulk 制造商:Cypress Semiconductor 功能描述:128K X 36 DUAL-PORT SRAM, 4.4 ns, PQFP176 |
| CY7C0852V-133AXC | 功能描述:IC SRAM 4MBIT 133MHZ 176LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C0852V-133AXCT | 功能描述:IC SRAM 4MBIT 133MHZ 176LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C0852V-133AXI | 功能描述:IC SRAM 4MBIT 133MHZ 176LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
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