參數(shù)資料
型號: CY7C0852V
廠商: Cypress Semiconductor Corp.
英文描述: FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: FLEx36TM 3.3 32K/64K/128K/256K × 36同步雙口RAM
文件頁數(shù): 25/29頁
文件大?。?/td> 764K
代理商: CY7C0852V
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 25 of 29
MailBox Interrupt Timing
[46, 47, 48, 49, 50]
Switching Waveforms
(continued)
t
CH2
t
CL2
t
CYC2
CLK
L
t
CH2
t
CL2
t
CYC2
CLK
R
3FFFF
t
SA
t
HA
A
n+3
A
n
A
n+1
A
n+2
L_PORT
ADDRESS
A
m
A
m+4
A
m+1
3FFFF
A
m+3
R_PORT
ADDRESS
INT
R
t
SA
t
HA
t
SINT
t
RINT
Table 7. Read/Write and Enable Operation
(Any Port)
[1, 8, 51, 52]
Inputs
CE
0
Outputs
DQ
0
DQ
35
High-Z
Operation
OE
X
CLK
CE
1
X
R/W
X
H
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
D
IN
Write
L
L
H
H
D
OUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
Notes:
46. CE
= OE = ADS = CNTEN = LOW; CE
= CNTRST = MRST = CNT/MSK = HIGH.
47. Address “3FFFF” is the mailbox location for R_Port of a 9M device.
48. L_Port is configured for Write operation, and R_Port is configured for Read operation.
49. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
50. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
51. OE is an asynchronous input signal.
52. When CE changes state, deselection and Read happen after one cycle of latency.
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CY7C0850V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
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