參數資料
型號: CY7C0852V
廠商: Cypress Semiconductor Corp.
英文描述: FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: FLEx36TM 3.3 32K/64K/128K/256K × 36同步雙口RAM
文件頁數: 22/29頁
文件大小: 764K
代理商: CY7C0852V
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
Document #: 38-06070 Rev. *D
Page 22 of 29
Readback State of Address Counter or Mask Register
[34, 35, 36, 37]
Notes:
34. CE
= OE = B0 – B3 = LOW; CE
= R/W = CNTRST = MRST = HIGH.
35. Address in output mode. Host must not be driving address bus after t
CKLZ
in next clock cycle.
36. Address in input mode. Host can drive address bus after t
.
37. An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Switching Waveforms
(continued)
CNTEN
CLK
t
CH2
t
CL2
t
CYC2
ADDRESS
A
0
–A
16
ADS
A
n
Q
x-2
Q
x-1
Q
n
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
LOAD
EXTERNAL
ADDRESS
t
CD2
INTERNAL
ADDRESS
A
n+1
A
n+2
A
n
t
CKHZ
DATA
OUT
A
n*
Q
n+3
Q
n+1
Q
n+2
A
n+3
A
n+4
t
CKLZ
t
CA2
or t
CM2
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
EXTERNAL
相關PDF資料
PDF描述
CY7C0850V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850V-133AC FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850V-133AI FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850V-133BBC FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850V-133BBI FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
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