參數(shù)資料
型號: CY7C0830AV
廠商: Cypress Semiconductor Corp.
英文描述: FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
中文描述: FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙口RAM(FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙端口RAM)的
文件頁數(shù): 21/28頁
文件大小: 775K
代理商: CY7C0830AV
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Document #: 38-06059 Rev. *Q
Page 21 of 28
Readback State of Address Counter or Mask Register
[42, 43, 44, 45]
Notes:
42.CE
= OE = BE0 – BE1 = LOW; CE
= R/W = CNTRST = MRST = HIGH.
43.Address in output mode. Host must not be driving address bus after t
CKLZ
in next clock cycle.
44.Address in input mode. Host can drive address bus after t
.
45.An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Switching Waveforms
(continued)
CNTEN
CLK
t
CH2
t
CL2
t
CYC2
ADDRESS
A
0
–A
16
ADS
A
n
Q
x-2
Q
x-1
Q
n
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
LOAD
EXTERNAL
ADDRESS
t
CD2
INTERNAL
ADDRESS
A
n+1
A
n+2
A
n
t
CKHZ
DATA
OUT
A
n*
Q
n+3
Q
n+1
Q
n+2
A
n+3
A
n+4
t
CKLZ
t
CA2
or t
CM2
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
EXTERNAL
相關PDF資料
PDF描述
CY7C0831AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0832AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0833AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0837AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0851V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K x 36同步雙端口RAM)
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