參數資料
型號： CY7C0830AV
廠商： Cypress Semiconductor Corp.
英文描述： FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
中文描述： FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙口RAM（FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙端口RAM）的
文件頁數： 12/28頁
文件大小： 775K
代理商： CY7C0830AV
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Document #: 38-06059 Rev. *Q
Page 12 of 28
Maximum Ratings
[22]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential...............–0.5V to +4.6V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to V
DD
+ 0.5V
DC Input Voltage...............................–0.5V to V
DD
+ 0.5V
[23]
Electrical Characteristics
Over the Operating Range
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage...........................................> 2000V
(JEDEC JESD22-A114-2000B)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
DD
Commercial
Industrial
3.3V±165 mV
3.3V±165 mV
Parameter
Description
-167
-133
-100
Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
V
OH
Output HIGH Voltage
(V
DD
= Min., I
OH
= –4.0 mA)
Output LOW Voltage
(V
DD
= Min., I
OL
= +4.0 mA)
Input HIGH Voltage
2.4
2.4
2.4
V
V
OL
0.4
0.4
0.4
V
V
IH
V
IL
I
OZ
I
IX1
I
IX2
I
CC
2.0
2.0
2.0
V
Input LOW Voltage
0.8
0.8
0.8
V
μ
A
μ
A
Output Leakage Current
–10
10
–10
10
–10
10
Input Leakage Current Except TDI, TMS, MRST
–10
10
–10
10
–10
10
Input Leakage Current TDI, TMS, MRST
–0.1
1.0
–0.1
1.0
–0.1
1.0
mA
Operating Current for
(V
= Max., I
OUT
= 0 mA), Outputs
Disabled
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
225
300
225
300
mA
CY7C0833AV
270
400
200
310
mA
I
SB1[24]
Standby Current
(Both Ports TTL Level)
CE
L
and CE
R
≥
V
IH
, f = f
MAX
Standby Current
(One Port TTL Level)
CE
L
| CE
R
≥
V
IH
, f = f
MAX
Standby Current
(Both Ports CMOS Level)
CE
L
and CE
R
≥
V
DD
– 0.2V, f = 0
Standby Current
(One Port CMOS Level)
CE
L
| CE
R
≥
V
IH
, f = f
MAX
Operating Current
(V
DD
= Max, I
OUT
= 0 mA, f = 0)
Outputs Disabled
90
115
90
115
90
115
mA
I
SB2[24]
160
210
160
210
160
210
mA
I
SB3[24]
55
75
55
75
55
75
mA
I
SB4[24]
160
210
160
210
160
210
mA
I
SB5
CY7C0833AV
70
100
70
100
mA
Notes:
22.The voltage on any input or I/O pin can not exceed the power pin during power-up.
23.Pulse width < 20 ns.
24.I
SB1
, I
SB2
, I
SB3
and I
SB4
are not applicable for CY7C0833AV because it can not be powered down by using chip enable pins.
相關PDF資料
PDF描述
CY7C0831AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0832AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0833AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0837AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
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