- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379052 > CY7C0831AV (Cypress Semiconductor Corp.) FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) PDF資料下載
參數(shù)資料
| 型號： | CY7C0831AV |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) |
| 中文描述： | FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙口RAM（FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙端口RAM）的 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 775K |
| 代理商： | CY7C0831AV |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Cypress Semiconductor Corporation
Document #: 38-06059 Rev. *Q
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 10, 2006
Features
True dual-ported memory cells that allow simultaneous
access of the same memory location
Synchronous pipelined operation
Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit
devices
Pipelined output mode allows fast operation
0.18-micron CMOS for optimum speed and power
High-speed clock to data access
3.3V low power
— Active as low as 225 mA (typ)
— Standby as low as 55 mA (typ)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
120TQFP (14 mm x 14 mm x 1.4 mm)
Lead(Pb)-free packages available
Counter wrap around control
— Internal mask register controls counter wrap-around
— Counter-interrupt flags to indicate wrap-around
— Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual Chip Enables on both ports for easy depth
expansion
Functional Description
The FLEx18 family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit
and 9-Mbit pipelined, synchronous, true dual-port static RAMs
that are high-speed, low-power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location
by more than one port at the same time is undefined. Registers
on control, address, and data lines allow for minimal set-up
and hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal Write pulse width is
independent of the duration of the R/W input signal. The
internal Write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0833AV device in this family has limited features.
Please
see
Address
Counter
Operations
[15]
on page 6 for details.
and
Mask
Register
Table 1. Product Selection Guide
Density
512-Kbit
(32K x 18)
CY7C0837AV
167
4.0
225
144 FBGA
1-Mbit
(64K x 18)
CY7C0830AV
167
4.0
225
120 TQFP
144 FBGA
2-Mbit
(128K x 18)
CY7C0831AV
167
4.0
225
120 TQFP
144 FBGA
4-Mbit
(256K x 18)
CY7C0832AV
167
4.0
225
120 TQFP
144 FBGA
9-Mbit
(512K x 18)
CY7C0833AV
133
4.7
270
144 FBGA
Part Number
Max. Speed (MHz)
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V
FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18
Synchronous Dual-Port RAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C0832AV | FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) |
| CY7C0833AV | FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) |
| CY7C0837AV | FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM) |
| CY7C0851V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K x 36同步雙端口RAM) |
| CY7C0852V | FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0831AV-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 2.25MBIT 128KX18 4.4NS 120TQFP - Trays |
| CY7C0831AV-133AXI | 功能描述:靜態(tài)隨機存取存儲器 2MB (128Kx18) 3.3v 133MHz Synch 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C0831AV-133BBC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C0831AV-133BBI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0831AV-133BBXI | 功能描述:靜態(tài)隨機存取存儲器 Flex18 2M IND Sync DualPort RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。