參數(shù)資料
型號: CY7C0831AV
廠商: Cypress Semiconductor Corp.
英文描述: FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
中文描述: FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙口RAM(FLEx18 3.3 64K/128K × 36和128K/256K × 18同步雙端口RAM)的
文件頁數(shù): 16/28頁
文件大?。?/td> 775K
代理商: CY7C0831AV
CY7C0837AV
CY7C0830AV/CY7C0831AV
CY7C0832AV/CY7C0833AV
Document #: 38-06059 Rev. *Q
Page 16 of 28
Switching Waveforms
Master Reset
Read Cycle
[11, 29, 30, 31, 32]
Notes:
29.OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
30.ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
31.The output is disabled (high-impedance state) by CE = V
following the next rising edge of the clock.
32.Addresses do not have to be accessed sequentially since ADS = CNTEN = V
IL
with CNT/MSK = V
IH
constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
MRST
t
RSR
t
RS
INACTIVE
ACTIVE
TMS
TDO
INT
CNTINT
t
RSF
t
RSS
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
t
CH2
t
CL2
t
CYC2
t
SC
t
HC
t
SW
t
SA
t
HW
t
HA
A
n
A
n+1
CLK
CE
R/W
ADDRESS
DATA
OUT
OE
A
n+2
A
n+3
t
SC
t
HC
t
OHZ
t
OE
t
OLZ
t
DC
t
CD2
t
CKLZ
Q
n
Q
n+1
Q
n+2
1 Latency
BE0–BE1
t
SB
t
HB
相關(guān)PDF資料
PDF描述
CY7C0832AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0833AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0837AV FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM(FLEx18 3.3V 64K/128K x 36和128K/256K x 18同步雙端口RAM)
CY7C0851V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K x 36同步雙端口RAM)
CY7C0852V FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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