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參數(shù)資料
| 型號： | CY62177DV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (2M x 8) Static RAM |
| 中文描述： | 16兆位（2米× 8）靜態(tài)RAM |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 856K |
| 代理商： | CY62177DV30 |
Document #: 001-07721 Rev. *B
Page 7 of 10
CY62168EV30 MoBL
Figure 3
shows WE controlled write cycle waveforms.
[14, 18, 19]
Figure 3. Write Cycle No. 1
Figure 4
shows
CE
1
or CE
2
controlled write cycle waveforms.
[14, 18, 19]
Figure 4. Write Cycle No. 2
Switching Waveforms
(continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
VALID DATA
NOTE 20
CE
1
ADDRESS
CE
2
WE
DATA IO
OE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
VALID DATA
t
SA
NOTE 20
CE
1
ADDRESS
CE
2
WE
DATA IO
OE
Notes
18.Data IO is high impedance if OE = V
IH
.
19.If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high impedance state.
20.During this period the IOs are in output state. Do not apply input signals.
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| CY62177DV30L-55BAI | 制造商:Cypress Semiconductor 功能描述: |
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| CY62177DV30L-70BAIES | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62177DV30LL5-55BAXI | 制造商:Cypress Semiconductor 功能描述: |
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