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參數(shù)資料
| 型號(hào)： | CY62177DV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (2M x 8) Static RAM |
| 中文描述： | 16兆位（2米× 8）靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 856K |
| 代理商： | CY62177DV30 |
Document #: 001-07721 Rev. *B
Page 4 of 10
CY62168EV30 MoBL
Thermal Resistance
[9]
Parameter
Θ
JA
Description
Test Conditions
BGA
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit
board
55
Θ
JC
Thermal Resistance
(Junction to Case)
16
°
C/W
AC Test Loads and Waveforms
Parameters
R1
R2
R
TH
V
TH
2.5V (2.2V to 2.7V)
16600
15400
8000
1.2
3.0V (2.7V to 3.6V)
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR[8]
Description
Conditions
Min
1.5
Typ
[3]
Max
3.6
10
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V
CE
1
> V
CC
0.2V or CE
2
< 0.2V
V
IN
> V
CC
0.2V or V
IN
< 0.2V
t
CDR[9]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
t
R[10]
t
RC
ns
Data Retention Waveform
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
V
TH
Equivalent to:
THé VENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Fall time: 1 V/ns
Rise Time: 1 V/ns
V
CC(min)
t
R
V
CC(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
CE
1
or
V
CC
CE
2
Note
10.Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC
(min) > 100
μ
s or stable at V
CC
(min)
>
100
μ
s.
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相關(guān)PDF資料 |
PDF描述 |
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| CY62177DV30L-55BAI | 16-Mbit (2M x 8) Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY62177DV30L-55BAI | 制造商:Cypress Semiconductor 功能描述: |
| CY62177DV30L-55BAIES | 制造商:Cypress Semiconductor 功能描述: |
| CY62177DV30L-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3V 32M-Bit 2M x 16 70ns 48-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:SLOW 3.0V SUPER LOW POWER 2 MEG X 16 SRAM - Bulk |
| CY62177DV30L-70BAIES | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY62177DV30LL5-55BAXI | 制造商:Cypress Semiconductor 功能描述: |
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