參數(shù)資料
型號(hào): CY62167E
廠商: Cypress Semiconductor Corp.
英文描述: Replacement for National Semiconductor part number 9328FMQB. Buy from authorized manufacturer Rochester Electronics.
中文描述: 16兆位(1米× 16 / 2米× 8)靜態(tài)RAM
文件頁數(shù): 5/12頁
文件大?。?/td> 441K
代理商: CY62167E
CY62167E MoBL
Document #: 001-15607 Rev. *A
Page 5 of 12
Switching Characteristics
Over the Operating Range
[13, 14]
Parameter
Description
45 ns
Unit
Min
Max
READ CYCLE
t
RC
Read Cycle Time
45
ns
t
AA
Address to Data Valid
45
ns
t
OHA
Data Hold from Address Change
10
ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid
45
ns
t
DOE
OE LOW to Data Valid
22
ns
t
LZOE
OE LOW to LOW-Z
[15]
5
ns
t
HZOE
OE HIGH to High-Z
[15, 16]
18
ns
t
LZCE
CE
1
LOW and CE
2
HIGH to Low-Z
[15]
CE
1
HIGH and CE
2
LOW to High-Z
[15, 16]
10
ns
t
HZCE
18
ns
t
PU
CE
1
LOW and CE
2
HIGH to Power Up
0
ns
t
PD
CE
1
HIGH and CE
2
LOW to Power Down
45
ns
t
DBE
BLE/BHE LOW to Data Valid
45
ns
t
LZBE
BLE/BHE LOW to Low-Z
[15]
10
ns
t
HZBE
WRITE CYCLE
[17]
BLE/BHE HIGH to HIGH-Z
[15, 16]
18
ns
t
WC
Write Cycle Time
45
ns
t
SCE
CE
1
LOW and CE
2
HIGH
to Write End
35
ns
t
AW
Address Setup to Write End
35
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Setup to Write Start
0
ns
t
PWE
WE Pulse Width
35
ns
t
BW
BLE/BHE LOW to Write End
35
ns
t
SD
Data Setup to Write End
25
ns
t
HD
Data Hold from Write End
0
ns
t
HZWE
WE LOW to High-Z
[15, 16]
18
ns
t
LZWE
WE HIGH to Low-Z
[15]
10
ns
Notes
13.Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of V
CC
(typ)/2, input pulse levels
of 0 to V
(typ), and output loading of the specified I
/I
as shown in
“AC Test Loads and Waveforms” on page 4
.
14.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
application note AN13842
for further clarification.
15.At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
16.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
17.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE or BLE or both = V
, and CE
= V
. All signals must be active to initiate
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the write.
[+] Feedback
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CY62167EV18LL-558VXI 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
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