參數(shù)資料
型號(hào): CY62157EV18
廠商: Cypress Semiconductor Corp.
英文描述: 8-Mbit (512K x 16) Static RAM
中文描述: 8兆位(為512k × 16)靜態(tài)RAM
文件頁(yè)數(shù): 3/12頁(yè)
文件大?。?/td> 414K
代理商: CY62157EV18
CY62157EV18 MoBL
Document #: 38-05490 Rev. *D
Page 3 of 12
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................–65°C to + 150°C
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Supply Voltage to Ground
Potential...............................–0.2V to 2.45V (V
CCmax
+ 0.2V)
DC Voltage Applied to Outputs
in High-Z State
[4, 5]
..............–0.2V to 2.45V (V
CCmax
+ 0.2V)
DC Input Voltage
[4, 5]
.........–0.2V to 2.45V (V
CCmax
+ 0.2V)
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(in accordance with MIL-STD-883, Method 3015)
Latch-up Current ...................................................> 200 mA
Operating Range
Device
Range
Ambient
Temperature
V
CC
[6]
CY62157EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
Electrical Characteristics
(Over the Operating Range)
Parameter
Description
Test Conditions
55 ns
Unit
Min
Typ
[2]
Max
V
OH
Output HIGH Voltage
I
OH
= –0.1 mA
V
CC
= 1.65V
1.4
V
V
OL
Output LOW Voltage
I
OL
= 0.1 mA
V
CC
= 1.65V
0.2
V
V
IH
Input HIGH Voltage
V
CC
= 1.65V to 2.25V
1.4
V
CC
+ 0.2V
V
V
IL
Input LOW Voltage
V
CC
= 1.65V to 2.25V
–0.2
0.4
V
I
IX
Input Leakage
Current
GND < V
I
< V
CC
–1
+1
μ
A
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
, Output Disabled
–1
+1
μ
A
I
CC
V
CC
Operating Supply
Current
f = f
max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
18
25
mA
f = 1 MHz
1.8
3
mA
I
SB1
Automatic CEPower Down
Current–CMOS Inputs
CE
1
> V
CC
0.2V or CE
2
< 0.2V
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V)
f = f
max
(Address and Data Only),
f = 0 (OE, WE, BHE and BLE), V
CC
= V
CC(max)
.
2
8
μ
A
I
SB2 [7]
Automatic CE Power Down
Current–CMOS Inputs
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= V
CC(max)
.
2
8
μ
A
Capacitance
[8]
Parameter
C
IN
C
OUT
Description
Test Conditions
Max
10
10
Unit
pF
pF
Input Capacitance
Output Capacitance
T
A
= 25°C, f = 1 MHz, V
CC
= V
CC(typ)
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
IH(max)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100
μ
s ramp time from 0 to V
CC
(min) and 200
μ
s wait time after V
CC
stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
spec. Other inputs can be left floating.
8. Tested initially and after any design or process changes that may affect these parameters.
[+] Feedback
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