參數(shù)資料
型號(hào): CY62147DV30L-70BVI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4-Mbit (256K x 16) Static RAM
中文描述: 256K X 16 STANDARD SRAM, 70 ns, PBGA48
封裝: 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
文件頁數(shù): 4/12頁
文件大?。?/td> 418K
代理商: CY62147DV30L-70BVI
CY62147DV30
Document #: 38-05340 Rev. *D
Page 4 of 12
Data Retention Waveform
[12]
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10.Test condition for the 45 ns part is a load capacitance of 30 pF.
11.Full device operation requires linear V
ramp from V
to V
> 100
μ
s or stable at V
> 100
μ
s.
12.BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Capacitance
(for all packages)
[9]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
10
pF
C
OUT
Output Capacitance
10
pF
Thermal Resistance
[9]
Parameter
Description
Test Conditions
BGA
TSOP II
Unit
Θ
JA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
72
75.13
°
C/W
Θ
JC
Thermal Resistance
(Junction to Case)
8.86
8.95
°
C/W
AC Test Loads and Waveforms
[10]
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
3.0V
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.
[5]
Max.
Unit
V
DR
I
CCDR
V
CC
for Data Retention
Data Retention Current
1.5
V
μ
A
V
CC
= 1.5V
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
L
9
LL
6
t
CDR[9]
t
R[11]
Chip Deselect to Data Retention Time
0
ns
Operation Recovery Time
t
RC
ns
V
CC
V
CC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
V
Equivalent to:
THé ENIN EQUIVALENT
R
TH
ALL INPUT PULSES
R1
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
V
CC
CE or
BHE.BLE
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