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參數(shù)資料
| 型號： | CY62138VNLL-70BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 8 Static RAM |
| 中文描述： | 256K X 8 STANDARD SRAM, 70 ns, PBGA36 |
| 封裝： | 7 X 7 MM, 1.20 MM HEIGHT, FBGA-36 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CY62138VNLL-70BAI |
CY62138VN MoBL
Document #: 001-06513 Rev. **
Page 5 of 8
Read Cycle No. 2
[5., 11, 12]
Write Cycle No. 1 (WE Controlled)
[5, 8, 13, 14]
Write Cycle No. 2 (CE Controlled)
[5, 8, 13, 14]
Notes:
12.Address valid prior to or coincident with CE transition LOW.
13.Data I/O is high impedance if OE = V
.
14.If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15.During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
I
CC
I
SB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
SUPPLY
CURRENT
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATA
IN
VALID
NOTE 15
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA I/O
ADDRESS
CE
DATA
IN
VALID
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