參數(shù)資料
型號(hào): CY62138VNLL-70BAI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 256K x 8 Static RAM
中文描述: 256K X 8 STANDARD SRAM, 70 ns, PBGA36
封裝: 7 X 7 MM, 1.20 MM HEIGHT, FBGA-36
文件頁(yè)數(shù): 4/8頁(yè)
文件大小: 410K
代理商: CY62138VNLL-70BAI
CY62138VN MoBL
Document #: 001-06513 Rev. **
Page 4 of 8
Switching Waveforms
Read Cycle No. 1
[10, 11]
Switching Characteristics
Over the Operating Range
[4]
Parameter
Description
CY62138VN
Min.
Unit
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[6]
OE HIGH to High-Z
[6, 7]
CE LOW to Low-Z
[6]
CE HIGH to High-Z
[6, 7]
CE LOW to Power-up
CE HIGH to Power-down
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
35
5
25
10
25
0
70
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[6, 7]
WE HIGH to Low-Z
[6]
70
60
60
0
0
50
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
10
Notes:
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
7. t
, t
, and t
are specified with C
= 5 pF as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
10.Device is continuously selected. OE, CE = V
IL
.
11.WE is HIGH for read cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
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