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參數(shù)資料
| 型號： | CY62138VNLL-70BAI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 8 Static RAM |
| 中文描述： | 256K X 8 STANDARD SRAM, 70 ns, PBGA36 |
| 封裝： | 7 X 7 MM, 1.20 MM HEIGHT, FBGA-36 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CY62138VNLL-70BAI |
CY62138VN MoBL
Document #: 001-06513 Rev. **
Page 3 of 8
AC Test Loads and Waveforms
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC
typ., and output loading of the specified
I
/I
and 30-pF load capacitance.
5. CE is the combination of both CS
1
and CS
2
.
R1
R2
R
TH
V
TH
Value
1105
1550
645
1.75
Unit
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
Conditions
[4]
Min.
1.0
Typ.
[1]
Max.
3.6
5
Unit
V
μ
A
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.0V
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
No input may exceed
V
CC
+0.3V
0.1
t
CDR[3]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
ns
t
R
100
ms
Data Retention Waveform
[5]
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5 ns
< 5 ns
OUTPUT
V
Equivalent to:
THé VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
V
CC(min.)
t
R
V
CC(min.)
t
CDR
V
DR
> 1.0V
DATA RETENTION MODE
CE
V
CC
[+] Feedback
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