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參數(shù)資料
| 型號(hào)： | CY62138EV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mbit (256K x 8) MoBL㈢ Static RAM |
| 中文描述： | 2兆位（256K × 8）的MoBL㈢靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | CY62138EV30 |
CY62138EV30
MoBL
Document #: 38-05577 Rev. *A
Page 5 of 9
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
Switching Characteristics
(Over the Operating Range)
[9]
Parameter
Description
45 ns
Unit
Min.
Max.
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[10]
OE HIGH to High Z
[10,11]
CE LOW to Low Z
[10]
CE HIGH to High Z
[10, 11]
CE LOW to Power-up
CE HIGH to Power-up
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
10
45
22
5
18
10
18
0
45
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[10, 11]
WE HIGH to Low Z
[10]
45
35
35
0
0
35
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18
10
Notes:
9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2,
input pulse levels of 0 to V
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
10.At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
HZWE
is less than t
LZWE
for any given device.
11.t
, t
, and t
transitions are measured when the output enter a high-impedance state.
12.The internal write time of the memory is defined by the overlap of WE, CE = V
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
13.Device is continuously selected. OE, CE = V
IL
.
14.WE is HIGH for read cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62138EV30_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256K x 8) MoBL Static RAM |
| CY62138EV30_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2 Mbit (256K x 8) MoBL Static RAM |
| CY62138EV30_1106 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256 K x 8) MoBL Static RAM Automatic power down when deselected |
| CY62138EV30_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256 K ?? 8) MoBL Static RAM |
| CY62138EV30LL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256 K x 8) MoBL Static RAM Automatic power down when deselected |
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