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參數(shù)資料
| 型號(hào)： | CY62138FV30LL-45SXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2-Mbit (256K x 8) Static RAM |
| 中文描述： | 256K X 8 STANDARD SRAM, 45 ns, PDSO32 |
| 封裝： | 0.450 INCH, LEAD FREE, SOIC-32 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 930K |
| 代理商： | CY62138FV30LL-45SXI |
Cypress Semiconductor Corporation
Document #: 001-08029 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised March 26, 2007
CY62138FV30 MoBL
2-Mbit (256K x 8) Static RAM
Features
Very high speed: 45 ns
Wide voltage range: 2.20V–3.60V
Pin compatible with CY62138CV25/30/33
Ultra low standby power
— Typical standby current: 1
μ
A
— Maximum standby current: 5
μ
A
Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
Easy memory expansion with CE
1
, CE
2,
and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin
SOIC, 32-pin TSOP I and 32-pin STSOP packages
Functional Description
[1]
The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Place the device into standby
mode reducing power consumption when deselected (CE
1
HIGH or CE
2
LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
0
through IO
7
) is then written into the location
specified on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
0
through IO
7
) are placed
in a high impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
S
POWER
DOWN
WE
OE
A
A
A
A
R
COLUMN DECODER
256K x 8
ARRAY
DATA IN DRIVERS
A
CE1
CE2
A
Note
1. For best practice recommendations, refer to the Cypress application note
“System Design Guidelines”
at
http://www.cypress.com.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62138FV30LL-45SXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 5.0V SUPER LO PWR 128Kx16 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62138FV30LL-45XZKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY62138FV30LL-45ZAXA | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2 MB 256Kb x 8 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62138FV30LL-45ZAXAT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2 Mb 256Kb x 8 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62138FV30LL-45ZAXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 SLO 5.0V SUPER LO PWR 128Kx16 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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