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參數(shù)資料
| 型號(hào)： | CY62138EV30 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mbit (256K x 8) MoBL㈢ Static RAM |
| 中文描述： | 2兆位（256K × 8）的MoBL㈢靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 427K |
| 代理商： | CY62138EV30 |
2-Mbit (256K x 8) MoBL
Static RAM
CY62138EV30
MoBL
Cypress Semiconductor Corporation
Document #: 38-05577 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 14, 2006
Features
Very high speed: 45 ns
— Wide voltage range: 2.20V – 3.60V
Pin-compatible with CY62138CV30
Ultra-low standby power
—
Typical standby current: 1
μ
A
—
Maximum standby current: 7
μ
A
Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
Easy memory expansion with CE
and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Offered in Pb-free 36-ball BGA package
Functional Description
[1]
The CY62138EV30 is a high-performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption when deselected
(CE HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
COLUMN
R
S
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
CE
A
1
A
1
A
1
A
1
A
1
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|---|---|
| CY62138EV30LL-45BVXI | 2-Mbit (256K x 8) MoBL㈢ Static RAM |
| CY62138FV30 | 2-Mbit (256K x 8) Static RAM |
| CY62138FV30LL-45BVXI | 2-Mbit (256K x 8) Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62138EV30_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256K x 8) MoBL Static RAM |
| CY62138EV30_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2 Mbit (256K x 8) MoBL Static RAM |
| CY62138EV30_1106 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256 K x 8) MoBL Static RAM Automatic power down when deselected |
| CY62138EV30_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256 K ?? 8) MoBL Static RAM |
| CY62138EV30LL | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2-Mbit (256 K x 8) MoBL Static RAM Automatic power down when deselected |
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