參數(shù)資料
型號(hào): CY62137FV30
廠商: Cypress Semiconductor Corp.
英文描述: 2-Mbit (128K x 16) Static RAM(2Mbit (128K x 16)靜態(tài)RAM)
中文描述: 2兆位(128K的× 16)靜態(tài)隨機(jī)存儲(chǔ)器(2Mbit的(128K的× 16),靜態(tài)內(nèi)存)
文件頁(yè)數(shù): 4/12頁(yè)
文件大?。?/td> 511K
代理商: CY62137FV30
CY62137FV30 MoBL
Document Number: 001-07141 Rev. *E
Page 4 of 12
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters
.
Parameter
Θ
JA
Description
Test Conditions
VFBGA
75
TSOP II
77
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still air, soldered on a 3 × 4.5 inch,
two layer printed circuit board
Θ
JC
10
13
°
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveform
Parameters
R1
R2
R
TH
V
TH
2.5V (2.2V to 2.7V)
16667
15385
8000
1.20
3.0V (2.7V to 3.6V)
1103
1554
645
1.75
Unit
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ
[1]
Max
Unit
V
DR
I
CCDR [7]
V
CC
for Data Retention
Data Retention Current
1.5
V
V
CC
= 1.5V, CE > V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Ind’l/Auto-A
4
μ
A
Auto-E
12
t
CDR [8]
t
R [9]
Chip Deselect to Data Retention Time
0
ns
Operation Recovery Time
t
RC
ns
Data Retention Waveform
Figure 4. Data Retention Waveform
[10]
V
CC
V
CC
OUTPUT
R2
30 pF
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
Equivalent to: THéVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
V
INCLUDING
JIG AND
SCOPE
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
t
R
V
CC
CE or
BHE.BLE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear V
ramp from V
to V
> 100
μ
s or stable at V
> 100
μ
s.
10.BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
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