參數(shù)資料
型號(hào): CY62137FV30
廠商: Cypress Semiconductor Corp.
英文描述: 2-Mbit (128K x 16) Static RAM(2Mbit (128K x 16)靜態(tài)RAM)
中文描述: 2兆位(128K的× 16)靜態(tài)隨機(jī)存儲(chǔ)器(2Mbit的(128K的× 16),靜態(tài)內(nèi)存)
文件頁(yè)數(shù): 3/12頁(yè)
文件大?。?/td> 511K
代理商: CY62137FV30
CY62137FV30 MoBL
Document Number: 001-07141 Rev. *E
Page 3 of 12
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ...........................................................-0.3V to 3.9V
DC Voltage Applied to Outputs
in High Z state
[4, 5]
............................................-0.3V to 3.9V
DC Input Voltage
[4, 5]
.......................................–0.3V to 3.9V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch up Current ....................................................> 200 mA
Operating Range
Device
Range
Ambient
Temperature
–40°C to +85°C 2.2V to 3.6V
–40°C to +125°C
V
CC
[6]
CY62137FV30LL Ind’l/Auto-A
Auto-E
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
45 ns (Ind’l/Auto-A)
Min Typ
[1]
55 ns (Auto-E)
Min Typ
[1]
Unit
Max
Max
V
OH
Output HIGH Voltage
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output disabled
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1mA
2.0
2.0
V
2.4
2.4
V
V
OL
Output LOW Voltage
0.4
0.4
V
0.4
0.4
V
V
IH
Input HIGH Voltage
1.8
V
CC
+ 0.3 1.8
V
CC
+ 0.3 2.2
0.6
V
CC
+ 0.3
V
CC
+ 0.3
0.6
V
2.2
V
V
IL
Input LOW Voltage
–0.3
–0.3
V
–0.3
0.8
–0.3
0.8
V
μ
A
μ
A
I
IX
I
OZ
Input Leakage Current
–1
+1
–4
+4
Output Leakage
Current
–1
+1
–4
+4
I
CC
V
CC
Operating Supply
Current
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
13
18
15
25
mA
1.6
2.5
2
3
I
SB1
Automatic CE Power
Down Current – CMOS
Inputs
CE > V
CC
0.2V,
V
IN
> V
CC
– 0.2V, V
IN
< 0.2V
f = f
max
(address and data only),
f = 0 (OE, WE, BHE, and BLE), V
CC
= 3.60V
1
5
1
20
μ
A
I
SB2 [7]
Automatic CE Power
Down Current – CMOS
Inputs
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= 3.60V
1
5
1
20
μ
A
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
C
IN
C
OUT
Description
Test Conditions
Max
10
10
Unit
pF
pF
Input Capacitance
Output Capacitance
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Notes
4. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
5. V
=V
+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100
μ
s ramp time from 0 to V
(min) and 200
μ
s wait time after V
stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the I
SB2
/ I
CCDR
specification. Other inputs can be left floating.
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