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參數(shù)資料
| 型號： | CY505YC64DTT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 BROADWATER 64TSSOP |
| 標準包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:24 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400.9MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應商設(shè)備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
CY505YC64D
....................Document #: 001-03543 Rev *E Page 16 of 24
.
PD_RESTORE
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the CY505 will initiate a full reset. The results of this will
be that the clock chip will emulate a cold power on start and
go to the ‘Latches Open’ state. If the PD_RESTORE bit is set
to a ‘1’ then the configuration is stored upon PWRDWN#
asserted LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to
a ‘1’ then the PD_RESTORE bit must be ignored. In other
words, in Intel iAMT mode, PWRDWN# reset is not allowed.
FS_ A , FS_ B ,F S _ C ,FS_ D
CK _ P W R G D
P W RG D_ V R M
V DD C lo c k G e n
Clo c k S ta te
C lo c k O u tputs
Clo c k V C O
0.2-0.3 m S
De la y
Sta te 0
S ta te 2
S ta te 3
Wa it fo r
V T T_ P W RG D#
Sa m p le Se ls
Off
On
Sta te 1
D e vic e is n o t affe cted,
V T T_ P W RG D# is ig n o re d
Figure 7. CK_PWRGD Timing Diagram
Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#
PCI_STOP# Asserted
CPU_STOP# Asserted
SMBus OE Disabled
Single-ended Clocks Stoppable
Driven Low
Running
Driven Low
Non Stoppable
Running
Differential Clocks
Stoppable
Clock Drive High
Clock Driven Low
Clock# Driven Low
Non Stoppable
Running
Table 7. Output Driver Status
All Single-ended Clocks
All Differential Clocks except CPU1
CPU1
w/o Strap
w/Strap
Clock
Clock#
Clock
Clock#
Latches Open State
Low
Hi-Z
Low
Powerdown
Low
M1
Low
Running
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