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參數(shù)資料
| 型號(hào)： | CY505YC64DTT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 BROADWATER 64TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:24 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400.9MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
CY505YC64D
....................Document #: 001-03543 Rev *E Page 19 of 24
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
The device will operate reliably with
input duty cycles up to 30/70 but the
REF clock duty cycle will not be within
specification
47.5
52.5
%
TPERIOD
XIN Period
When XIN is driven from an external
clock source
69.841
71.0
ns
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-
s duration
–
500
ps
LACC
Long-term Accuracy
–
300
ppm
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at 0V differential @ 0.1s
45
55
%
TPERIOD
100 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
9.99900
10.0100
ns
TPERIOD
133 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
7.49925
7.50075
ns
TPERIOD
166 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
5.99940
6.00060
ns
TPERIOD
200 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
4.99950
5.00050
ns
TPERIOD
266 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
3.74963
3.75038
ns
TPERIOD
333 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
2.99970
3.00030
ns
TPERIOD
400 MHz CPUT and CPUC Period
Measured at 0V differential @ 0.1s
2.49975
2.50025
ns
TPERIODSS
100 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
9.99900
10.0100
ns
TPERIODSS
133 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
7.49925
7.50075
ns
TPERIODSS
166 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
5.99940
6.00060
ns
TPERIODSS
200 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
4.99950
5.00050
ns
TPERIODSS
266 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
3.74963
3.75038
ns
TPERIODSS
333 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
2.99970
3.00030
ns
TPERIODSS
400 MHz CPUT and CPUC Period, SSC
Measured at 0V differential @ 0.1s
2.49975
2.50025
ns
TPERIODAbs
100 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
9.91400
10.0860
ns
TPERIODAbs
133 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
7.41425
7.58575
ns
TPERIODAbs
166 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
5.91440
6.08560
ns
TPERIODAbs
200 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
4.91450
5.08550
ns
TPERIODAbs
266 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
3.66463
3.83538
ns
TPERIODAbs
333 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
2.91470
3.08530
ns
TPERIODAbs
400 MHz CPUT and CPUC Absolute period
Measured at 0V differential @ 1 clock
2.41475
2.58525
ns
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
9.91400
10.1363
ns
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
7.41425
7.62345
ns
TPERIODSSAbs 166 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
5.91440
6.11576
ns
TPERIODSSAbs 200 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
4.91450
5.11063
ns
TPERIODSSAbs 266 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
3.66463
3.85422
ns
TPERIODSSAbs 333 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
2.91470
3.10038
ns
TPERIODSSAbs 400 MHz CPUT and CPUC Absolute period, SSC Measured at 0V differential @ 1 clock
2.41475
2.59782
ns
TCCJ
CPUT/C Cycle to Cycle Jitter
Measured at 0V differential
–
85
ps
TCCJ2
CPU2_ITP Cycle to Cycle Jitter
Measured at 0V differential
–
125
ps
LACC
Long-term Accuracy
Measured at 0V differential
–
100
ppm
TSKEW2
CPU2_ITP to CPU0 Clock Skew
Measured at 0V differential
–
150
ps
TR/TF
CPUT and CPUC Rise and Fall Time
Measured differentially from ±150 mV
2.5
8
V/ns
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