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參數(shù)資料
| 型號： | CY505YC64DTT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CK505 BROADWATER 64TSSOP |
| 標準包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:24 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400.9MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應商設(shè)備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
CY505YC64D
....................Document #: 001-03543 Rev *E Page 20 of 24
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
245
550
mV
SRC
TDC
SRCT and SRCC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SRCT and SRCC Period
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRCT and SRCC Period, SSC
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODAbs
100 MHz SRCT and SRCC Absolute Period
Measured at 0V differential @ 1 clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz SRCT and SRCC Absolute Period,
SSC
Measured at 0V differential @ 1 clock
9.87400
10.1763
ns
TSKEW(window) Any SRCT/C to SRCT/C Clock Skew from the
earliest bank to the latest bank
Measured at 0V differential
–
3.0
ns
TCCJ
SRCT/C Cycle to Cycle Jitter
Measured at 0V differential
–
125
ps
LACC
SRCT/C Long Term Accuracy
Measured at 0V differential
–
100
ppm
TR/TF
SRCT and SRCC Rise and Fall Time
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
250
550
mV
DOT
TDC
DOT96T and DOT96C Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
DOT96T and DOT96C Period
Measured at 0V differential @ 0.1s
10.4156
10.4177
ns
TPERIODAbs
DOT96T and DOT96C Absolute Period
Measured at 0V differential @ 0.1s
10.1656
10.6677
ns
TCCJ
DOT96T/C Cycle to Cycle Jitter
Measured at 0V differential @ 1 clock
–
250
ps
LACC
DOT96T/C Long Term Accuracy
Measured at 0V differential @ 1 clock
–
300
ppm
TR/TF
DOT96T and DOT96C Rise and Fall Time
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
LCD_100_SSC
TDC
SSCT and SSCC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SSCT and SSCC Period
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SSCT and SSCC Period, SSC
Measured at 0V differential @ 0.1s
9.99900
10.0010
ns
TPERIODAbs
100 MHz SSCT and SSCC Absolute Period
Measured at 0V differential @ 1 clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz SRCT and SRCC Absolute Period,
SSC
Measured at 0V differential @ 1 clock
9.87400
10.1763
ns
TCCJ
SSCT/C Cycle to Cycle Jitter
Measured at 0V differential
–
250
ps
LACC
SSCT/C Long Term Accuracy
Measured at 0V differential
–
300
ppm
TR/TF
SSCT and SSCC Rise and Fall Time
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
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