參數(shù)資料
型號(hào)： CY505YC64DT
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 12/24頁(yè)
文件大?。?/td> 0K
描述： IC CLK CK505 BROADWATER 64TSSOP
標(biāo)準(zhǔn)包裝： 28
類型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
主要目的： Intel CPU 服務(wù)器
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:24
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 400.9MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TFSOP （0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 64-TSSOP
包裝： 管件
CY505YC64D
......................Document #: 001-03543 Rev *E Page 2 of 24
Pin Definitions
Pin No.
Name
Type
Description
1
PCI_0/OE#_0/2_A
I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 0 or
SRC 2. Default PCI0
2
VDD_PCI
PWR
3.3V Power supply for PCI PLL.
3
PCI_1/OE#_1/4_A
I/O, SE 33 MHz clock/3.3V OE# Input mappable via I2C to control either SRC 1 or
SRC 4. Default PCI1.
4
PCI_2/TME
I/O, SE 3.3V tolerance input for overclocking enable pin 33 MHz clock.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
5
PCI_3/FSD
I/O, SE,
PD
3.3V tolerant input for CPU frequency selection/33 MHz clock.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
6
PCI_4/SRC5_SEL
I/O, SE 3.3V tolerant input to enable SRC5/33 MHz clock output.
(sampled on the CK_PWRGD assertion)
1 = SRC5, 0 = CPU_STOP#
7
PCIF_0/ITP_EN
I/O, SE
PD
3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output.
(sampled on the CK_PWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND
Ground for outputs.
9
VDD_48
PWR
3.3V Power supply for outputs and PLL.
10
USB_48/FSA
I/O
3.3V tolerant input for CPU frequency selection/fixed 48 MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
11
VSS_48
GND
Ground for outputs.
12
VDD_IO
PWR
0.7V Power supply for outputs.
13, 14
SRCT0/DOT96T
SRCC0/DOT96C
O, DIF 100 MHz Differential serial reference clocks/Fixed 96 MHz clock output.
Selected via I2C default is SRC0.
15
VSS_IO
GND
Ground for PLL2.
16
VDD_PLL3
PWR
3.3V Power supply for PLL3
17, 18
SRCT1/LCDT_100/25M
SRCC1/LCDC_100
O, DIF,
SE
100 MHz Differential serial reference clocks/100 MHz LCD video clock/25 MHz
SATA clock. Default LCD
19
VSS_PLL3
GND
Ground for PLL3.
20
VDD_PLL3_IO
PWR
0.7V Power supply for PLL3 outputs.
21, 22
SRCT/C[2]/SATA
O, DIF 100 MHz Differential serial reference clocks.
23
VSS_SRC
GND
Ground for outputs.
24, 25
SRCT3/OE#_0/2_B
SRCC3/OE#_1/4_B
I/O,
Dif
100-MHz Differential serial reference clocks/3.3V OE#_0/2_B, input,
mappable via I2C to control either SRC 0 or SRC 2/3.3V OE#_1/4_B input,
mappable via I2C to control either SRC 1 or SRC 4. Default SRC3
26
VDD_SRC_IO
PWR
0.7V power supply for SRC outputs.
27, 28
SRCT/C[4]
O, DIF 100 MHz Differential serial reference clocks.
29
VSS_SRC
GND
Ground for outputs.
30, 31
SRCT/C[9]
O, DIF 100 MHz Differential serial reference clocks.
33, 32
SRCT11/OE#_10
SRCC11/OE#_9
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#9 Input controlling
SRC9/3.3V OE#10 Input controlling SRC10. Default SRC11.
34, 35,
SRCT/C[10]
O, DIF 100 MHz Differential serial reference clocks.
36
VDD_SRC_IO
PWR
0.7V Power supply for SRC outputs.
38, 37
SRCT5/PCI_STOP#
SRCC5/CPU_STOP#
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs/3.3V tolerant input for
stopping CPU outputs/100 MHz Differential serial reference clocks. Default
SRC5
39
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
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