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參數(shù)資料
| 型號： | CY2LL842 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 196K |
| 代理商： | CY2LL842 |
CY2LL8422
Document #: 38-07411 Rev. **
Page 8 of 12
Notes:
4.
5.
6.
7.
8.
9.
All input pulses are supplied by a frequency generator with the following characteristics: t
R
& t
F
≤
1nS; Pulse rep rate = 50 Mpps; Pulse width = 10
±
0.2 ns.
RL = 100 Ohm.
CL includes instrumentation and fixture capacitance within 6 mm of the DUT.
VOC measurement requires equipment with a 3-dB bandwidth of at least 300 MHz.
RL = 100 Ohm ±1%.
Point to Point: RL = 100 Ohm ±1% CL 3 pF.
A
B
R
Pulse
Generator
Y
Z
10 pF
DE
D
CL = 10pF
RL
0.0V
100%
80%
20%
0%
tR
tF
V
I(A)
V
I(B)
1.4V
1.0V
Figure 6. Test Circuit & Voltage Definitions for the
Differential Output Signal
[4,5,6]
Y
Z
10 pF
DE
D
CL = 10pF
RL
A
B
R
Pulse
Generator
Voc (ss)
V
DD
Voc (pp)
V
I(A)
V
I(B)
1.4V
1.0V
Figure 7. Test Circuit & Voltage Definitions for the Driver
Common-Mode Output Voltage
[4,5,6,7]
Y
Z
10 pF
10 pF
RL & RC
DE
A
B
R
Pulse
Generator
D
1.4 V
1.4 V
1.0 V
0V Differential
1.2 V C M
1.2 V C M
VIB
VIA
V0Y
V0Z
T
P LH
T
P HL
1.0 V
0V Differential
0V Differential
80%
20%
V 0Y - V 0Z
tR
tF
Figure 8. Differential Receiver to Driver Propagation
Delay and Driver Transition Time
[4,8,9]
Y
Z
CL =10 pF
DE
A
B
R
1.0 V or 1.2V
D
1.2V
1.2V
T
PHZ
T
PLZ
T
PZH
1.2V
1.2V
1.0V
1.4V
1.25V
1.15V
2.0V
1.4V
V0Y or V0Z
V0Y or V0Z
DE
0.8V
T
PZL
Figure 9. Test Circuit & Voltage Definitions for the Driver
Common-Mode Output Voltage
[4,8]
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