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參數(shù)資料
| 型號： | CY28547LFXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 18/24頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK505/410M INTEL 72QFN |
| 標(biāo)準(zhǔn)包裝： | 240 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:23 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
CY28547
.......................Document #: 001-05103 Rev *B Page 3 of 24
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
32
PCI2/TME
I/O, SE 33-MHz clock output/Trusted Mode Enable Strap
Strap at pin 39 assertion to determine if the part is in trusted mode or not.
Internal pull-up resistor of 100K to 3.3V, use 10K resistor to pull it low externally
if needed
0 = Normal mode
1= Trusted mode (default)
33
PCI3
O, SE 33-MHz clock output
34
PCI4/FCTSEL1
I/O
33-MHz clock output/3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on pin 39 assertion).
Internal pull-down resistor of 100K to GND
37
ITP_SEL/PCIF0
I/O,SE 3.3V LVTTL input to enable SRC10 or CPU2_ITP/33-MHz clock output. (sampled
on pin 39 assertion).
Internal pull-down resistor of 100K to GND
1 = CPU2_ITP, 0 = SRC10
39
VTT_PWRGD#/PD
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe. When asserted, according
to the polarity defined by pin 9 (PGMODE), it latches data on the FSA, FSB, FSC,
FCTSEL1 and ITP_SEL pins. After assertion, it becomes a real time input for
controlling power down.
40
VDD_48
PWR
3.3V power supply for outputs.
41
48M/FSA
I/O
Fixed 48-MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
42
VSS_48
GND
Ground for outputs.
43, 44
DOT96T/ 27M_NSS
DOT96C/ 27M_SS
O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output Selected
via FCTSEL1 at pin 39 assertion.
45
FSB/TEST_MODE
I
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when
in test mode
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
47, 48
SRC[T/C]0/
LCD100M[T/C]
O,DIF 100-MHz differential serial reference clock output/Differential 96/100-MHz SS
clock for flat-panel display
Selected via FCTSEL1 at pin 39 assertion.
50, 51
SRCT_1/SATAT,
SRCC_1/SATAC
O, DIF 100-MHz Differential serial reference clocks.
Pin Description (continued)
Pin No.
Name
Type
Description
FCTS E L1 P in 43
P in 44
P in 47
P in 48
0 DOT96T
DOT96C
96/100M_T 96/100M_C
1 27M_NSS
27M_SS
SRCT0
SRCC0
PGMODE
Pin 39
0
0 = POWER GOOD (VTT_PWRGD#)
0
1 = POWER DOWN (PD)
1
0 = POWER DOWN (PD#)
1
1 = POWER GOOD (CKPWRGD)
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