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參數(shù)資料
| 型號(hào)： | CY28547LFXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK505/410M INTEL 72QFN |
| 標(biāo)準(zhǔn)包裝： | 240 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:23 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
CY28547
.....................Document #: 001-05103 Rev *B Page 24 of 24
Document History Page
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon
Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of
information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters.
Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application
or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.
Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other
application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should
Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon
Laboratories harmless against all claims and damages.
Document Title: CY28547 Clock Generator for IntelCK410M/CK505
Document Number: 001-05103
REV.
Issue Date
Orig. of
Change
Description of Change
1.0
See ECN
RGL
New data sheet
1.1
See ECN
RGL/XLZ
Modify the definition of pin 9, 27, 32 and 39
Re-arrange control register map
Update AC Electrical Specifications table
1.2
See ECN
RGL
Modify the pin description table
Update the default values in the control register bytes 7, 8, 9, 11, 12, 14, and 15
1.3
12/28/06
JMA
1. Modified Revision ID Bit from 0010 to 0011
2. Set Byte 12 <7> from DIAG_EN to Reserved
3. Set Byte 12 <6> from CPU_PLL Status to Reserved
4. Set Byte 12 <5> from Video_PLL Status to Reserved
5. Set Byte 12 <4> from Fixed_PLL Status to Reserved
6. Edited Figure 15 and 16 Terminationa Resistor for double load 12-ohm to
22-ohm
7. Edited Figure 15 and 16 Load from 5pF to 4pF.
8. Changed CPU Vox_min from 250ps to 300ps
9. Changed SRC Vox_min from 180ps to 300ps
10. Changed LCD Vox_min from 250ps to 300ps
11. Changed DOTVox_min from 250ps to 300ps
1.4
10/31/07
JMA
Added Mitsui package
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28547LFXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK505 Mobile System Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28548ZXC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Intel 960/965M Crest line CK505 Intg Vreg RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28548ZXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Intel 960/965M Crest line CK505 Intg Vreg RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28551 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Generator for Intel, VIA, and SIS㈢ |
| CY28551-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Generator for Intel, VIA and SIS㈢ |
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