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參數(shù)資料
| 型號： | CY28410ZXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK410GRANTSDALE 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:19 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 266MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SLCY28410ZXCT |
CY28410
........................Document #: 38-07593 Rev. *C Page 6 of 17
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
0
Reserved
Reserved, Set = 0
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, Set = 0
6
0
DOT96[T/C]
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5
0
PCIF2
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
4
0
PCIF1
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
3
0
PCIF0
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
2
1
Reserved
Reserved, Set = 1
1
Reserved
Reserved, Set = 1
0
1
Reserved
Reserved, Set = 1
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C][7:0]
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
6
0
Reserved
Reserved, Set = 0
5
0
Reserved
Reserved, Set = 0
4
0
Reserved
Reserved, Set = 0
3
0
SRC[T/C][7:0]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
REF/N or Hi-Z Select
1 = REF/N Clock, 0 = Hi-Z
6
0
Test Clock Mode Entry Control
1 = REF/N or Hi-Z mode, 0 = Normal operation
5
0
Reserved
Reserved, Set = 0
4
1
REF
REF Output Drive Strength
0 = Low, 1 = High
3
1
PCIF, SRC, PCI
SW PCI_STP# Function
0=SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description
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